CS122A Fall Quarter, 1998

Lab 5: Introduction to VHDL Simulation and Synthesis
Prof. Frank Vahid

Purpose:
The purpose of this lab is to introduce you to VHDL simulation and synthesis using the ALDEC VHDL simulator and the Xilinx foundation software for synthesis. In this lab, you will implement a behavioral description of a 2-bit counter whose output is fed to a 2-4 decoder. As a result, the top level entity should be structural containing the two components: 2-bit counter and 2-4 decoder.

Description:
A behavioral style architecture specifies what a particular system does but provides no information on how the design is implemented.
A testbench would verify that the behavior of the system is as expected. We then need to translate the design description to another level of abstraction, i.e, from behaviour to structure. This process of translation is called synthesis and can be achieved by using a Synthesis tool like Foundation Express which outputs a netlist. It is similar to the compilation of a high level programming language like C into assembly code.
In this lab, you will specify an entity and test it, synthesize your design using FPGA Express and download it onto an XS40 board using the Xilinx Foundation software.

Assignment:

1. Describe a 2-bit counter and a 2-4 decoder in VHDL. Construct a top-level structural entity containing these two components. Write a suitable testbench and simulate it to ensure that it is correct. If you need information on how to use the ALDEC VHDL simulator, see the tutorial.
2. Synthesize the design unto the XS40 boards using the Xilinx Foundation FPGA software.

Schematic:

--
-- Tony Givargis, Roman Lysecky
--
--*******************************************************************

library IEEE;
use IEEE.STD_LOGIC_1164.all;
use IEEE.STD_LOGIC_ARITH.all;

--*******************************************************************

entity XS40 is
   port( clk : in STD_LOGIC;
         rst : in STD_LOGIC;
         output : out UNSIGNED(3 downto 0) );
end XS40;

--*******************************************************************

architecture XS40_ARCH of XS40 is

   --
   -- insert component declarations here
   --

   --
   -- insert signal declarations here
   --

begin

   --
   -- instantiate and map components here
   --

end XS40_ARCH;

--******************************************************************

Steps to be Followed:

1. Complete the code and test the functionality using ALDEC VHDL. Show the TA the waveforms.
2. Complete the wrled.vhd code. You may find the 7-segement display useful.
3. Run through the XS40 board tutorial and see if you can get the XS40 board to count.
   (Note: Jumper on J4 needs to be set when loading the program but disconnected when running the program.)
4. Wire up the circuit as shown. You may need the circuit diagram or the the manual for the XS40 boards.
5. Make the neccessary additions to your lab5.ucf file.
6. Download your program unto the XS40 board.

Conclusion:
You are to demonstrate your implementations to the TA and submit a lab report with your VHDL code attached.