Homework 4
UCR CS122A Embedded Systems Design, Prof. Frank Vahid, Fall 2000
Due: Wednesday, Nov. 29, 3:00 p.m., in the bin OUTSIDE my office (Bourns A207).

ESD refers to the book Embedded Systems Design by Vahid/Givargis

1. Compose 2kx16 ROM's into an 8kx24 ROM. Yes, you'll have unused outputs.
   Label all wires or groups of wires VERY CLEARLY; there should be
   no ambiguities. Assume the 2kx16 ROM's have a chip enable. Be sure
   your 8kx24 ROM also has a chip enable input.

2. ESD Ch5 Excercise 8.

3. ESD Ch6 Excercise 2. 

4. Design a simple DMA controller that supports transfers from a single 
   peripheral to memory.  The DMA controller should have three internal 
   registers: PBASE is the start address in the peripheral, 
   MBASE is the start address in the memory, and BLOCK is the size of the
   block of data to transfer. (a) Use an FSMD to describe this DMA 
   controller. (b) Convert this FSMD to an FSM and structural datapath. 
   Do NOT design structure for the FSM.
   
5. Using a 4-port 8051, show how to extend the number of ports to 8 by using
   extended parallel I/O. Be specific. Show the extended parallel I/O device
   interface clearly (you can assume you have such a device available, but
   make any assumptions you make as to its interface clear).   Show the
   C code necessary to write to the additional ports. Remember that you
   will be using up some of your 8051 ports to interface with this
   extended parallel I/O device!

6. Analyze the average and worst-case response time for the following
   system. Four peripherals A, B, and C compete for bus access using a 
   priority arbiter. Assume servicing a peripheral requires 1 ms. 
   A requests servicing every 2 ms; if it doesn't get serviced right
   away, those requests will be queued up internally. Likewise, B
   requests every 3 ms, and C every 4 ms. Assume the microprocessor can 
   instantly respond and begin servicing a request.  Provide the average 
   and worst-case servicing response times (the time each peripheral must 
   wait before its request gets serviced, caused by the microprocessor being 
   busy servicing another peripheral) for each peripheral, assuming
   (a) fixed priority arbitration, with A having highest priority, followed 
       by B, and then C. 
   (b) rotating priority arbitation, with priority initially being 
       A,B,C, then B,C,A, then C,A,B, then back to A,B,C. The priority 
       rotates after each servicing, independent of who gets serviced.
   (c) least-recently-serviced-first priority arbitration, where the device
       that was least-recently serviced has highest priority, and the
       device that was most-recently serviced has lowest priority.
   Show all work, state any assumptions! 
   HINT: draw a time line and fill in the scheduling of servicing, until
   you see a steady-state pattern develop (if it does indeed develop).