Homework 4
UCR EE/CS120B: Intro. to Embedded Systems
Winter Quarter 2002, Prof. F. Vahid
Due Thursday, March 14 at beginning of lecture

1. ESD 5.1

2. ESD 5.7

3. A 64Kbit instruction memory holds 16-bit words. (Figure out how many 
   words and how many address lines does that memory has.)
   The memory has a read time of 10 clock cycles.
   A processor uses a (trivially small) direct-mapped instruction cache with 
   4 rows, using the low-order address bits to index into the cache, and 
   the high-order bits as the tag. Assume a block size of 1. The cache
   has a read time of 1 cycle for a hit.  On a miss, the cache waits 
   an additional 10 cycles to read the instruction from memory to cache, 
   and then returns the instruction 1 cycle later, for a total read time of 
   12 cycles for a miss.  
   
   (a) Assuming the cache is initially empty, show its contents for the 
   following sequence (called a trace) of addresses being read: 

      1, 2, 3, 1, 1, 1, 9, 1, 9, 9, 9
   
   (b) Compare the total time for the above address trace for a system
   with the cache and without. 

4. ESD 6.2   

5. ESD 6.6

6. ESD 6.7