Homework 2
UCR EE/CS120B: Introduction to Embedded Systems
Winter Quarter 2002, Prof. Frank Vahid
Due Jan 24 before lecture



1. Design a 4-bit register implementing the following specifications:
     Inputs:   I3, I2, I1, I0, clk, S1, and S0
     Outputs:  O3, O2, O1, O0
     Function: S1 S0 = 0  0 -- maintain current value
                     = 0  1 -- load I as new current value
                     = 1  0 -- increment current value (rolls over to 0)
                     = 1  1 -- clear current value to 0
               The O signals should always output the current value. 
     Guidelines: Use 4 D flip-flops, multiplexors, and minimal additional
                 logic.
                 The clk input should be input directly to all flip-flops
                 without going through any logic. 

2. Redesign the above register so that it has the following inputs:
     I3, I2, I1, I0, clk, load, inc, clear
   The meaning of the last three signals should be obvious. If two or
   three of those signals are asserted in the same clock cycle, the 
   register should simply maintain its current state.

3. (a) Design a 4-bit counter implementing the following specifications:
     Inputs:   I3, I2, I1, I0, clk, inc, dec
     Outputs:  TC, O3, O2, O1, O0
     Function: inc = 1 -- add 1 (roll over to 0000 if at 1111)
               dec = 1 -- subtract 1 (roll over to 1111 if at 0000)
               If both inc and dec are 1, just maintain current value
               The O signals should output the current value. 
               The TC signal should be 1 for one cycle if inc=1 and we 
                  reach 1111, or if dec=1 and we reach 0000.
     Guidelines: Use 4 D flip-flops, multiplexors, and minimal additional
                logic. The clk input should be input directly to flip-flops.
   (b) Show how to cascade two such counters to create an 8-bit counter. 

4. ESD 2.12 (counter design for a sequence of numbers).

5. Design a bus bridge that does the opposite of the bridge in ESD Fig 2.13;
   namely, it receives an 8-bit value and sends two 4-bit values in sequence.
   Start with an FSMD and show all design steps, including the design of the
   FSM controller (using a ROM to implement the control logic). 

6. ESD 2.19. Recall that the Fibonacci number F(n) is formed by summing
   F(n-1) and F(n-2), and that F(0)=0 and F(1)=1. Design a circuit whose
   input n is 4 bits wide, and whose output should be F(n). You determine
   how wide this output and your datapath components need to be.