CS122A
Fall Quarter, 1999


CS122A LAB SCHEDULE

In the following schedule, the "Assigned" column indicates when the TA will formally describe each lab, and the "Due" column indicates the very latest that each lab must be demo'ed -- lab reports are due at the time of the demo, not after. HOWEVER, you should plan to work AHEAD of this schedule, starting before the assigned dates and demo'ing before the due dates. You can demo a lab any time that the TA is available. You should make full use of the 4 hours of every lab session, either working ahead on assigned labs, or developing your final project. Students should NOT be leaving the lab sessions early except for rare personal circumstances.

Date Assigned Due
Week 0
January 3-7
Session 1

Session 2 NO LABS

Week 1
January 10-14
Session 1 Lab Orientation
Lab 1A: Intro to FPGA's with schematic capture
Lab 1A: Intro to FPGA's with schematic capture
Session 2 Lab 1B: Intro to FPGA's using VHDL
Week 2
January 17-21
Session 1 Lab 2: Synthesis Lab 1B: Intro to FPGA's using VHDL
Session 2
Lab 2: Synthesis
Week 3
January 24-28
Session 1 Lab 3: ALU Design
Session 2
Lab 3: ALU Design
Week 4
January 31-Feburary 4
Session 1 Lab 4: 4-bit Counter
Session 2

Week 5
Feburary 7-11
Session 1
Lab 4: 4-bit Counter
Session 2 Lab 5: FSM+D Design
Week 6
Feburary 14-18
Session 1

Session 2
Lab 5: FSM+D Design
Week 7
Feburary 21-25
Session 1 Lab 6: Microprocessor
Lab Quiz (in Lecture)

Session 2

Week 8
Feburary 28-March 3
Session 1

Session 2

Week 9
March 6-March 10
Session 1
Lab 6: Microprocessor
Session 2 NO LABS
Week 10
March 13-March 17
Session 1 NO LABS
Session 2 NO LABS