UCR EE/CS120B: Digital Systems

UCR EE/CS120B: Digital Systems, Winter 2000, Home Page

Course objective

To learn to design digital systems at the register and processor levels, emphasizing modern CAD tools.

Course information

Instructor: Frank Vahid (vahid@cs.ucr.edu). Office hours TR 2-3, Bourns A207

Lecture TR 11:10-12:30, OLMH 1208 (course call# 16139)

Labs (Bourns B252) sec 021 (16140) WF 6:10-10
sec 022 (16141) MW 2:10-6
sec 023 (16142) TR 6:10-10

Prerequisites EE/CS120A

Textbooks
Gajski, Principles of Digital Design, Prentice Hall, ISBN 0-13-301144-5
VHDL source -- online sources listed below. For those serious about digital design, I suggest purchasing a VHDL book.
NOTE: if you need a book and the bookstore doesn't have one, use another source, such as the web or technical bookstores (see the yellow pages). You can order direct from most publishers too.

TA's lab: Leslie Tauro (stauro@cs),Michael Samidi (msamidi@cs), office hours during scheduled lab.
lecture: Lin Ling (lling@cs), office hours: W 2-4 in CS TA office
Questions/comments can be emailed to cs120b-t@cs, which automatically forwards to all TA's and lab assistants.

Grade 10% Homeworks, 20% Labs, 10% Lab exams, 40% Midterms, 20% Final.

Lecture overview

Combinational components (e.g., adders, ALUs, ROMs).

Sequential logic (e.g., FSMs, FSM synthesis, analysis).

Storage components (e.g., registers, counters, RAM, datapaths).

Processor design

Lab overview

Introduction to FPGA boards and VHDL

Introduction to synthesis from VHDL

FSM synthesis

FSMD synthesis

Processor synthesis

Notes

While lecture and lab material obviously overlap, the two aspects of the course are quite independent, with lectures dealing with general theory and principles, and lab dealing specifically with specific software and hardware. Exams will focus on lecture material, but may include some amount of lab material. Students in lab will work with one partner. Lab exams will be held during the quarter to ensure that all individuals are learning the lab material (i.e., that one is not relying too heavily on one's partner).

Important note on academic dishonesty: cheating will be punished severely. Every year there are several students who are caught copying on homeworks, exams and labs: they receive a harsh grade penalty (often an F in the course) and a letter is sent to the campus student conduct officer and kept on file (since repeat offenses may result in suspension or expulsion from UCR). There are two common responses by students caught cheating:

They made a mistake and now they've learned their lesson and so please don't impose the sanctions -- the answer is no, and you now know this answer beforehand.

They didn't know that their actions would be considered cheating (especially on homeworks) -- if you submit the same (or extremely similar) answer on a homework problem for which getting the same answer could only reasonably come from jointly solving the problem with another student, that's academic dishonesty.

For those of you who don't want others' cheating to cheapen your own hard work and your grade -- there is an anonymous cheating reporting form at: https://www.cs.ucr.edu/cheating/. While students may discuss material generally, homework submissions MUST represent independent work, and submissions MUST INCLUDE the following statement at the top: "This is my own original work." . This statement will contribute to each homework grade. It is your responsibility to be familiar with UCR's and the CS&E department's policies on academic dishonesty. See: http://www.cs.ucr.edu/curriculum/.

Submitted homeworks should be neat and legible -- a portion of each homework grade will consist of neatness and legibility. Furthermore, problems that are simply too messy will not be graded. You should submit homeworks that use a minimum number of pages -- 2 pages (front and back) should be sufficient for most homeworks -- excessively long homeworks will have points taken off. In most cases, the appropriate approach is to work out the problems on scratch paper, and then rewrite the problems neatly for submission.

Regrade policy: corrections to graded material must be submitted within one week of the distribution of the graded items. Corrections to grades database entries must also be corrected within one week of the grades being posted.

Email address: We maintain email addresses in the course database. It follows that you must provide us with a correct address, and that you must read your email regularly (roughly on a daily basis). Some announcements will be made via email. Also, your scores during the quarter will be sent to that email address.

Draft versions of upcoming labs are found below

Lab 1a: Intro to FPGA's w/schematic capture
Lab 1b: Intro to FPGA's using VHDL
Lab 2: Synthesis
Lab 3: ALU design
Lab 4: 4-bit counter
Lab 5: FSM plus datapath design
Lab 6: Microprocessor design

Lab guidelines

You should plan to stay for the duration of your 4-hour scheduled lab time. Labs are all posted on the web, so if you finish before a due date, you should proceed to work on the next lab. If it appears that students are leaving early, then measures may be taken.
Each lab assignment's grade will typically consist of your lab demo (simulation and board), and your lab report (writeup, source code and results).
No late lab submissions will be accepted.
Lab reports are due before the end of your scheduled lab time on the date you are checked off for your demo. Use the report form above. We will be using electronic turnin (see below).
The TA's will not be available for help 15 minutes before the end of each lab. This time is reserved for checking out completed labs.
The students are required to work in groups of two. Students are welcome to choose their own lab partners.
The TA's will check out the Xilinx boards to each group when required. Boards are only available during scheduled lab. Student must check the boards back in when done, and must be sure to sign the check in sheet. Students should also be sure the TA records your score your lab demo.
The Xilinx boards are pre wired. Please do not change any wiring unless specifically instructed by the TA.
You are required to go to the lab section you are registered in. If you wish to change your lab section, this must be pre-approved by the LECTURE TA.
The TA's and Lab Assistants will be there to assist you in any problems that you might face for the full four hours (except during the check off time). Please feel free to approach any of them with any problems or questions that you might have. If you have any problems or questions please email cs120b-t@cs.ucr.edu. One of the TA's will answer your question as soon as possible.
Any suggestions to help us improve the lab will be welcomed.

Electronic assignment turn-in

Important resources

I recommend that students interested in the digital systems field purchase the following:
Aldec VHDL simulator student edition
It's an easy to use yet powerful VHDL simulator written for Windows, and I think a great deal (around $50).
Xilinx Student Edition Software and FPGA Board. ( purchase options) ( purchase info). This would be very useful to anyone planning to do further work in digital design (e.g., as part of senior design projects). Cost is about $100.
Online VHDL tutorial
Online VHDL textbook: VHDL Cookbook
VHDL synthesis tutorial
(local copy of tutorial)
Online digital design textbook: Contemporary Logic Design

Some interesting related links

Xilinx University Program
Interview with Gordon Moore
Intel Museum (Intro's to transistors and microprocessors)
History of the transistor
ASICs textbook by Smith
Online VLSI Design Tutorial
Link to UCR EE/CS120A Pentium III design tradeoffs

Back to Frank Vahid's home page

Instructor:	Frank Vahid (vahid@cs.ucr.edu). Office hours TR 2-3, Bourns A207
Lecture	TR 11:10-12:30, OLMH 1208 (course call# 16139)
Labs (Bourns B252)	sec 021 (16140) WF 6:10-10 sec 022 (16141) MW 2:10-6 sec 023 (16142) TR 6:10-10
Prerequisites	EE/CS120A
Textbooks	Gajski, Principles of Digital Design, Prentice Hall, ISBN 0-13-301144-5 VHDL source -- online sources listed below. For those serious about digital design, I suggest purchasing a VHDL book. NOTE: if you need a book and the bookstore doesn't have one, use another source, such as the web or technical bookstores (see the yellow pages). You can order direct from most publishers too.
TA's	lab: Leslie Tauro (stauro@cs),Michael Samidi (msamidi@cs), office hours during scheduled lab. lecture: Lin Ling (lling@cs), office hours: W 2-4 in CS TA office Questions/comments can be emailed to cs120b-t@cs, which automatically forwards to all TA's and lab assistants.
Grade	10% Homeworks, 20% Labs, 10% Lab exams, 40% Midterms, 20% Final.