UCR EE/CS 120B   Digital Systems   Winter 2000 Professor Frank Vahid

Homework 1  Due: Tuesday, 1/25/00, BEFORE lecture.  You can turn it
in before lecture begins at 11:10, or put it under the door of
A207 before 11:00.  Remember to turn in a neat homework. 
Don't forget the required "This is my own original work" statement 
at the top. SHOW YOUR WORK for every problem.

1. Design a 4-bit register, using D flip-flops, with the following operations:
     s1 s0   operation
     --------------------
      0  0   No change
      0  1   Parallel load
      1  0   Synchronous clear (don't assume the flip-flop has asnych clear)
             You must load 0's through the mux for this operation!
      1  1   Increment (add 0001 to contents).
   Register inputs are d3, d2, d1, d0, s1, s0. Outputs are q3, q2, q1, q0.

   (Suggestion on how to work with others on this problem -- go over the 
   registers in the book until you understand all of them and know how to 
   use the mux in front of each flip-flop to implement different operations.  
   Build this register yourself with NO HELP from others. Check each others
   answers to see if they work.)  
   
2. Implement the following simple FSM. It has inputs I, and output Y.
   The FSM has 3 states. It stays in the first state until I=1, when
   it switches to the second state.  It stays in the second state as long
   as I stays 1; when I goes back to 0, it goes to the third state.
   It stays in the third state as long as I=0; when I goes back to 1,
   it switches to the first state again.
   (a) Draw the FSM
   (b) Draw the target architecture
   (c) Draw the state table
   (d) Minimize the logic and draw the final circuit.
       You may use a register with clearly labeled inputs and outputs.
   
3. Implement the following FSM using a register and combinational logic.
   The FSM recognizes a sequence of 3 ones. An input Reset resets the
   the FSM to its initial state. If at any time after the reset, three
   ones occur in a row (three consective clock cycles) on an input I, 
   the FSM sets its output Y to 1, and holds it at 1 until a reset 
   occurs again. So the following sequence results in Y=1 on the
   fifth cycle after reset: 0,0,1,1,1,0...
   But the following sequence does not: 0,0,1,1,0,1,0...

   (a) Start by drawing the FSM, (b) draw the target architecture,
   (c) draw the state table, (d) then minimize the logic and draw 
   the final complete circuit. 
   You don't need to design the register internals; just use a symbol 
   with clearly labeled inputs and outputs.
   
   To ensure your circuit works properly, analyze it (essentially, the
   above steps in reverse): (e) derive the next state and output equations,
   (f) draw the state table for these equations, (g) draw the state diagram
   and ensure it works.