In this lab you will implement a General Purpose Processor (GPP) using techniques we've learned so far. A GPP unlike a Single Purpose Processor can accomplish various tasks via programs written in an Instruction Set that the microprocessor can recognize. Most processors are built from a controller, dataptath and memory. For the purposes of this lab we will deviate from this processor architecture and have the memory integrated into the controller.

Description

The General Purpose Processor we will be building will have to recognize the following instruction set:

Note: A few of you may notice that the OPCODE and ADDRESS are both 4 bits wide. This would mean we would have a datapath that is only 4 bits. This is true. The input of the datapath (Data Memory) and output is only 4-bits wide. This means the ALU and registers are also 4-bits wide. Note: The LOAD Mem instruction is actually going to be loaded from an external location off of the XS40 board.

2) MOVR Rd 0001|dd00 Register [dd] = Accumulator

3) LOAD Mem 0010|mmmm Accumulator = Memory[mmmm]

*Note: Memory location 0 is actually the IN PORT of the XS40 board. So in essence we don't have Data Memory. You can use this instruction as a select on a MUX to pick the input port.

4) LOADI Imm 0011|iiii Accumulator = Immediate

*) *STORE Mem 0100|mmmm Memory[mmmm] = Accumulator

6) JZ Address 0101|0000 if (Acc == 0)
aaaa|aaaa PC = Address[aaaa] // goto address
else
NOP // do nothing

7) JMP Address 0110|0000 PC = Address[aaaa]
aaaa|aaaa

8) ADD Rd 0111|dd00 Accumulator = Accumulator + Register[dd]

9) ANDR Rd 1001|dd00 Accumulator = Accumulator AND Register[dd]

10) INV 1011|0000 Accumulator = NOT Accumulator

11) SHR 1010|0000 Accumulator = Accumulator >> 1

*) *SUB Rd 1000|dd00 Accumulator = Accumulator - Register[dd] 1111|1111

12) HALT 1111|1111 Stop execution

* Optional at this point. You DO NOT HAVE TO IMPLEMENT THESE 2 INSTRUCTIONS but are included so you can see what a complete instruction set might look like.

The following files contain VHDL code for a microprocessor that only operates on 2 instructions: LOADI and HALT.
When you download these you will need to rename them so the extensions are .vhd.
ctrl.vhd
datapath.vhd
cpu.vhd

Assignment

1. Take a look at the 3 files above and become familiarized with the structure of it. Your TA will give you a quick lecture on processor design and what you might need for your controller and datapath.

2. Using the above instruction set, write an algorithm that follows the one's count algortihm in the book on paper. The one's count algorithm counts how many 1's appear in a n-bit binary number. So for the number 0110, the output should be 2.

3. Implement the instruction set, one instruction at a time in your controller. In other words, grow your design one function/instruction at a time. Make sure the instruction works. Do this by deciding what your datapath needs for the one instruction and ADD the functionality to each component. Test it by hard-coding in 1 instruction, and simulate it.

*Note: The output should come from the Accumulator inside your datapath. This is because all the data movement/alu operations involve the Accumulator. By tieing the output to this at all times, we can see what is going on. Currently, the skeleton has the output of the alu, going straight to the output of the whole thing. You should change this.

The code for the Accumulator and Register File is included. You can write your own if you want but in either case you still need to figure out how to interconnect all these components. Yes, this is possible by implementing one funtion/instruction at a time. Do this by connecting only what you need per component. For instance, only use one register inside the register file...this way you can bypass the use of a select line at first. Understand? Don't connect everything given to you hoping it will work. We've purposely left out the needed interconnections in all 3 files so you can "GROW" your design.

For the time being, you do not have to synthesize your design but keep in mind we might change this.

4. Synthesize and download each modification on your design onto the FPGA following the instructions in the previous lab. You will need to create your own .ucf file for each modification. You can use the pins assigned in the previous labs.
5. Make sure it works.

6. Repeat step 3 for another instruction.

7. Implement the one's count algorithm inside your microprocessor. You should have this already done so all you have to do is basically program your microprocessor. Simulate the results. Download the design if time permitting.

DUE DATE: June 3rd and June 7th