UCR EE/CS120B: Digital Systems, Spring 1999

Lab 5 - 4-bit counter

For this lab, you are required to write a vhdl description of a finite state machine (FSM) and a testbench to show its correctness.

Inputs into your machine will be the following:

• clk - This signal will be used as a clock signal
• rst - This signal will be used to reset your machine when it goes to '1' (active high).
• Input - A 4-bit number that will be used to load a value into the counter.
• Up/Down - This indicates if the counter will be counting up or counting down. If this signal is high, the counter should count down. If the signal is low, the counter should count up.
• Load - A one bit signal that indicates when you should load a value into the counter from the inputs. When this value goes high, you will load the value on Input into the counter.
• Enable - If this signal is high, then the counter should count. If this signal is low, the counter should stop.

First come up with the FSM that will describe how this design should function. Next, translate that into a VHDL description as described in lab and finally test your design by writing a VHDL testbench and observing the results.