1. Start up Xilinx and select "Create a New Project" Save it in temp as before. Name it lab2 and select the "HDL" instead of the "Schematic Capture" option.
2. Click on the little paper icon in the "Design Entry" button. this should bring up the HDL editor. Choose "Empty Design".
3. Write all of the code to structurally implement the design from the previous lab. (Hint: The schematic should translate directly into this design only now you should have entities for each component, like an entity for a three input or gate and others).
4. Once you have all the program typed in goto "Synthesis" and select "Check Syntax". After ensuring that there are no syntax errors, go back to the "Project Manager".
5. Select the "Synthesis" step as the next step in the design process. Ensure that the "BCD" entity that you created is selected for the "Top LeveL", and that the Target Device information is as follows: "Family" = XC4000XL, "Device" = 4010XLPC84. Now click on "Run".
6. Now verify the correctness of your VHDL code, by selecting the "Simulation" button. Add the appropriate signals to your waveform, and their stimuli as you did in the previous laboratory assignment.