UCR EE/CS120B: Digital Systems, Spring 1999

Lab 1

Part 1 - Simulating your design

Steps:

1. Click on the Xilinx Foundation Software Icon on the desktop. The "Getting Started" window should pop up. Select the "Create a new project" option and then click on "OK".
2. Enter "lab1" as the project name, and change the directory name to "C:\temp". Select "XC4000XL", family for the FPGA, from the first drop-down menu at the bottom. And Select the "4010XLPC84", for the component number, from the second drop-down menu at the bottom. Ensure that the "Schematic" option is selected for the "flow" option. Click on "OK".
3. Click on the Schematic Editor in the Design Entry stage (Icon shaped like a gate) A new shematic editor window should now appear. Click on "Mode", and select "Symbols". A symbol window list should now pop up. The following truth table represents the functionality of a BCD to 7-segment decoder that you are designing:

           g
          ---
        f| d |e
          ---
        c|   |b
          ---  
           a
   
   
   IN1 IN2 IN3 IN4            a b c d e f g
   0    0   0   0             1 1 1 0 1 1 1 
   0    0   0   1             0 1 0 0 1 0 0 
   0    0   1   0             1 0 1 1 1 0 1 
   0    0   1   1             1 1 0 1 1 0 1 
   0    1   0   0             0 1 0 1 1 1 0 
   0    1   0   1             1 1 0 1 0 1 1 
   0    1   1   0             1 1 1 1 0 1 1 
   0    1   1   1             0 1 0 0 1 0 1 
   1    0   0   0             1 1 1 1 1 1 1 
   1    0   0   1             0 1 0 1 1 1 1 
   

   All the other values are don't cares (Since in a BCD, we should only have the values 0 through 9).
4. The next step is to generate the minimized equations for the outputs "a" through "g" using the Karnaugh map method you learned in CS120A.
5. Now that you have equations for the outputs "a" through "g", you must draw the schematic which must eventually be downloaded on to the XS40 board.
6. Click on the "Hierarchy Connector", which should result in a new pop-up window. In this window, for the inputs select "Input" for the "Terminal Type", and enter the appropriate terminal names ("IN1" through "IN4"). Select the "IBUF" for all of the four inputs from the symbol table, and connect each input to an "IBUF". Now generate the rest of the circuit according to your minimized equations.
7. Now Generate the outputs using the "Hierarchy Connector" as done in step 10, and do not forget to add the necessary "OBUF" before the output pads.
8. We are now ready for simulation. Save the file in your project directory, make sure that the filename is less than 5 characters in length, and then select "Options", and choose "Create Netlists". Following that, choose "Integrity Check" and finally select "Export Netlists". A window will pop-up at this point, select "Edit 200 [*.EDN]" in the "Files of Type" selection box. Now click on "Open", and the netlist will be exported. Select the "File" drop-down menu, and exit the schematic editor. Make "lab1.sch" a part of the schematic by selecting the "Document" drop-down menu, and click on "Add" to add your schematic to the list of schematics in the project. Now click on "Simulation" This will bring up the waveform viewer. At this point go to "Signal", and click on "Add Signals". Add only the input signals, and the output signals that you created in your schematic.
9. Now we need to apply simulators to the input signals to have interesting things happen to our output signals. Select the "Signal" drop-down menu, and select "Add Simulators" menu item. We are interested in the binary counter stimulus labeled "BC". Select the appropriate bits corresponding to the inputs in your design (ex: the LSB - least significant bit, should be connected to the least significant bit in your inputs). This is accomplished by selecting the input signal followed by the appropriate stimulus.
10. Once all of the inputs have been mapped, we need to set up a parameter that controls the speed of the simulation. Select the "options" drop-down menu followed by the "Preferences" menu item. Then in the preferences window set the appropriate values for the "B0 Period" and the "Simulation Precision" to obtain an easily viewable waveform.
11. Now select "Options" -> "Long Simulation" and enter the time-period for your simulation (eg: 2 seconds). After insuring the correctness of your output, contact either a TA or lab assistant to be checked-off for this portion of the laboratory assignment.