UCR EE/CS 120B   Digital Systems   Spring 1999  Professor Frank Vahid

Homework 1  Due: Tuesday, 4/13, BEFORE lecture.  You can turn it
in before lecture begins at 11:10, or put it under the door of
A207 before 11:00.  You must complete the following using two sides of 
only two stapled sheets of 8x11 paper (no perforated edges from spiral 
notebooks), Don't forget the required "This is my own original work"
statement at the top. SHOW YOUR WORK for every problem.

1. Design a 6x1 multiplexor using AND, OR, and INVERT gates.
   Include a truth table representing its functionality.
   Make use of don't cares if possible.  Draw the netlist as a schematic, 
   and also write a VHDL description of that netlist.

2. (a) Design a sprinkler controller that reads a 3-bit binary
   input, and asserts (sets to 1) exactly one output that would
   turn on one of 8 sprinklers.  Make sure to show a truth
   table as well as a circuit. (b) What common combinational
   component does the circuit represent?

3. Design an ALU that can perform add, subtract, decrement,
   AND, and XOR operations.  Use a table to indicate the operation
   for each combination of the ALU's control lines.  Draw a schematic
   of the internal netlist of the ALU.
   
4. (a) Design a 2-bit carry-lookahead (CLA) adder with carry input and carry 
       output.
   (b) Build an 8-bit adder by connecting four 2-bit CLA adders.

5. (a) Complete the table:
                                             delay        # gate inputs
      -----------------------------------------------------------------
      8-bit carry ripple adder                          |
      8-bit adder built from 2-bit CLA's                |
      8-bit CLA adder                                   |
 
      # gate inputs is the sum of the number of inputs to every gate.
      Compute delay assuming a 10 ns delay through each gate.

   (b) Show how you computed each of the 6 entries in the table.