UCR EE/CS 120B   Digital Systems   Spring 1998  Professor Frank Vahid

Homework 4  Due: Tuesday, 6/2, BEFORE lecture.  You can turn it
in before lecture begins at 11:10, or put it under the door of
A207 before 11:00.  You must complete the following using two sides of 
only TWO sheets of 8x11 paper (no perforated edges from spiral notebooks).
Write your name on both sheets.  Don't forget the required statement OF 
originality at the top of the first page.  Show your work for every problem.  

1. Problem 8.10 (Gajski)

2. You are to design a parallel to serial data conversion component (which is a 
   simple version of a UART -- Universal Asynchronous Receiver Transmitter).  The
   component has a 32-bit data input  data, a load control input  load,
   and a 1-bit data output  txd.  Initially, the component outputs a 1 on
    txd.  When  load becomes 1, the component stores  data internally
   and then outputs a 0 on  txd for exactly one clock cycle (representing the
   start bit.  Then, it outputs the 32 bit data, 1 bit per clock cycle starting
   with the least significant bit, over  txd.  After all 32 bits have been
   transmitted, the device returns to its initial state of outputing 1 (the stop bit)
   and waiting for the next load.  There must be at least 1 stop bit before the
   next data item is transmitted.   Design the component by creating the following:
   (a) an FSMD description of the system, (b) a custom datapath for your system,
   (c) an FSM to control your datapath, and (d) a complete final circuit. 
   Hint: include a shift register in your datapath, among other components.
   (Note: There are a wide variety of answers to this problem, so it is extremely 
   unlikely that two students would obtain the same answer.)