Soda Machine lab
I. Introduction
The purpose of this lab is to implement a soda machine. The cost of the soda
is $1.25. Your machine will accept quarters, dimes, and nickels. As the user
feeds coins into the machine you will need to keep track of how much was
inserted. Once you have collected at least $1.25, you will release a soda.
To simplify this lab you will not be required to give out change. There are
five inputs to the system and one output. They are as follows:
- enable: This basically acts as an on/off switch. When the
signal is low the circuit is "off".
- rst: This will clear the accumulator and reset release to
0.
- clk: This is the clock signal for the state machine and
any sequential component(s) of your datapath.
- quarter: This indicates the user has inserted 25 cents into
the machine and will increase the accumulator accordingly.
- dime: This indicates the user has inserted 10 cents into
the machine and will increase the accumulator accordingly.
- nickel: This indicates the user has inserted 5 cents into
the machine and will increase the accumulator accordingly.
- release: When this signal is set to 1, a soda will be
released. It has to be up for at least one clock cycle, but cannot stay up indefinately.
You will start with an FSMD then split it into a controller plus datapath
(FSM + D). The controller is an FSM which issues commands to the datapath based
on the current state and the external inputs. This can be a behavioral
description. The datapath contains a netlist of functional units like
multiplexors, registers, adders and comparator, so this design must be
structural.
II. Implementation
- On paper create an FSMD for your soda machine controller.
Remember, each state must set values for the outputs to the datapath
and the release output. The next state will depend on the inputs to
the soda machine as well as inputs from the datapath. This must
be checked by the TA before proceeding.
- Using section 2.4 of your Embedded Systems book, create an FSM and a datapath to implement your design
- Create the VHDL for each of the components in your datapath
(mux, adder, registers, etc).
- Write a testbench for each of the components and test them alone (not connected to anything else).
- Write the code for your FSM controller.
- Write a testbench for the controller alone and test it.
- Finish the design by creating an overall entity that connects everything.
- Write a test bench and verify the correctness of the whole thing and demo it to your TA. For full credit your testbench must include several cases and test each of the inputs (including enable and rst) and has to include asserts to insure that a soda is released at the correct time and is NOT released at an incorrect time. Also, be sure your code is well commented, including your name(s), lab number, and file name is at the top of each file.