Storage Components
I. Introduction
For this lab, you are required to write a VHDL description at the
behavioral level of a 4-byte register file and a 1-byte register with parallel
load/shift. Once you have these two components, you need to write a
testbench to show the correctness of each one.
For a general description of registers look in the Embedded Systems Design book on pages 34 and 35.
Register File
Size is 4 bytes, i.e. four rows of 8 bits. Each row (byte) is addressable.
The inputs, outputs, and functionality of the register file are as follows:
- clk: This signal will be used as a clock signal.
- data: The 8-bit write port that will be used to write a value
into the register file.
- readA: The first 8-bit read port that will be used to read a value
from the register file.
- readB: The second 8-bit read port that will be used to read a value
from the register file.
- WE: The write enable input.
- WA: The 2-bit address of the register to be written to if WE is high.
- RAE: The first read enable input.
- RAA: The 2-bit address of the register to be read from if RAE is high.
- RBE: The second read enable input.
- RBA: The 2-bit address of the register to be read from if RBE is high.
Parrallel Load/Shift Register
The inputs, outputs, and functionality of the parallel load/shift register are as follows:
- clk: This signal will be used as a clock signal.
- input: The 8-bit input.
- output: The 8-bit output.
- SH: The 2-bit load/shift select input.(00 = hold value; 01 = load input;
10 = shift left; 11 = shift right)
- If SH is 01 or 10 it will shift every clock cycle
II. Procedure
Implementation and simulation
- Write the behavioral description of the two components described above.
- Test your design by writing a VHDL testbench and observing the
results in ALDEC Active-VHDL.
- Your testbenches should contain many conditions and have asserts to ensure the correctness.