Synthesis:
Behavioral description of a 7-segment decoder

I. Introduction

The XS40 board uses a seven segment display. The inputs to the display correspond to each of the LEDs (Light Emitting Diodes). Therefore, we need a way to decode (ie translate) binary numbers to 7 bit numbers that correspond to the number being decoded. For example, if we wanted to display the number seven on the display, we would send the number 0111 to the decoder, and it determines which LEDs to turn on. We are going to display 16 numbers (zero through F), so we will need a four bit input. The purpose of this lab is to write code so that the 7-segment decoder is described behaviorally. To do this a distinction must be made between a behavioral description and a structural description.

Here is an example to get you started, and describe the difference between structural and behavioral:

Suppose we want to construct the above circuit. We can describe the circuit in several ways.

STRUCTURAL DESCRIPTION
If we were to describe the above circuit structurally we would first have to construct entities which act as AND2 and OR2 gates. Then we would plug our input values into these entities to get our result. 

...

entity NAND2 is
   port ( input1, input2: in STD_LOGIC;
          output1: out STD_LOGIC
        );
end NAND2;

architecture beh_nand2 of nAND2 is
begin
   output1 <= input1 nand input2;
end beh_nand2;



entity XOR2 is
   port ( input1, input2: in STD_LOGIC;
	  output1: out STD_LOGIC
        );
end XOR2;

architecture beh_xor2 of XOR2 is
begin
   output1 <= input1 xor input2;
end beh_xor2;



entity CIRCUIT is
   port ( a, b, c : in STD_LOGIC;
          f: out STD_LOGIC;
        );
end CIRCUIT;

architecture struct of CIRCUIT is

signal e: STD_LOGIC;

component NAND2
   port ( input1, input2: in STD_LOGIC;
          output1: out STD_LOGIC
        );
end component;

component XOR2
   port ( input1, input2: in STD_LOGIC;
          output1: out STD_LOGIC
        );
end component;

begin
   X1: NAND2 port map(A, B, E);   
   X2: XOR2 port map(E, D, F);

end struct;

...
BEHAVIORAL DESCRIPTION
If we were to describe the above circuit behaviorally we would not have to worry about mimicing the gates. Instead we can describe the result at a more abstract level which greatly simplifies things as seen below: 

...

entity CIRCUIT is
   port ( a, b, d: in STD_LOGIC;
	  f: out STD_LOGIC
        );
end CIRCUIT;

architecture beh of CIRCUIT is
begin
   f <= (a nand b) xor d;
end beh;

...

II. Procedure

Implement the entity

  1. Write your decoder behaviorally, and check it using Aldec Active-HDL. Refer to previous labs to help you get started using Aldec Active-HDL. You will be using this code in later labs, so make sure it is neat and easy to read.
  2. Write a testbench that checks all sixteen possible situations. If it is working correctly, demonstrate it to the TA.
  3. Make sure to copy both your design VHDL file and your testbench to your home directory or a disk.
  4. Open up Xilinx Foundation and start a design using your design VHDL file as the only file (you will not need the testbench here).

Creating and simulating the output of Xilinx

Xilinx synthesizes your design down to a level of basic building blocks.  It will create a VHDL file that represents what it thinks you want.  Conveniently, you can test this file with the same test-bench you created for your behavioral code.

  1. Create a new Project in Xilinx paying close attention to what directory it will be put in AND make sure to check the button for HDL
  2. Add your VHDL file to the project (don't add your testbench)
  3. Click on the Synthesis Block in the window on the right side (the top-level should be your top entity)
  4. Click "Run"
  5. Now click on the Implementation Block
  6. That should bring up a settings window.  At the bottom of it, click on "Options"
  7. For "Simulation" select "GenericVHDL"
  8. Click "OK" then click on "Run"
  9. After Xilinx finishes the process of placing and routing your design, look in the directory where your project is for a file named "time_sim.vhd"
  10. This part may get a little tricky:  You need to copy this file (time_sim) to your ActiveHDL project
  11. Now that it is in your ActiveHDL project add it to your design and look at the code.  It should be very long and look nothing like what you made
  12. Note the name of the new entity and change it in your testbench if necessary (it should still have the same inputs and outputs)
  13. re-simulate with this VHDL and there should be some very small differences.  
  14. Show this simulation to your TA
Generate the bit file and download unto an XS40 board
  1. Check out an XS40 board.
  2. Open up your project under Xilinx. Make sure that the names of your variables match exactly with those in the UCF (User Constraints File).
  3. Right click on the root of your project and select "Edit Constraints"  and replace it with decoder.ucf.
  4. Now you can run through the Implementation stage and generate a bit file as previously done in Lab 2a.
  5. Save the .bit file to your root directory.
  6. Make sure your XS40 board is powered up and connected to the computer.
  7. Use putty to connect to "Local Machine"
  8. Type "export XSTOOLS_BIN_DIR=/bin/."
  9. Load you bit file by typing "xsload decoder.bit" on the prompt (or whatever the name of your bit file is) and hit "enter". Verify your results.
  10. Test your code by toggling the dip switches and making sure the correct number appears on the display.
  11. If it is working, demonstrate it to your TA
  12. E-mail your lab report and code for both your design and testbench to your TA.