ALU design

I. Introduction

In this lab you are basically building a 2-bit ALU. You are required to write a behavioral description of an ALU. Note: when constructing the ALU, do not use LE's, AE's, and FA's as shown in the book. All you really need are case statements, etc ...


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The ALU should take in two 2-bit numbers and have the following functionality:

The output of the ALU will consist of one 2-bit result and a carry/borrow bit. You are also required to write a testbench for this design. You will have to feed values into your design and demonstrate that it is correct by simulating your desgin using ALDEC Active-VHDL--using the testbench you wrote.

Notes on design:
There are many ways to correctly implement this design. It will be easiest to NOT use the adder created in the tutorial.
You have to be careful to account for the carry bit and the borrow bit. You are subtracting B from A. Therefore, if B is bigger than A, the borrow bit will be one (the borrow bit is the sign bit in this instance).
When NOR'ing and AND'ing, the borrow bit will always be zero.

Notes on testbench:
Your testbench should show that the design works in a good sample of problems--proving that it works in every possible situation would be difficult.
For our purposes, you should test at least each of the functions (add, subtract, nor, nand) and situations that use the borrow and carry bits. For this design, a good testbench will have a minimum of eight different cases. If you want to make more, it shouldn't be too difficult using cut and paste with a few changes.

II. Procedure

Implementing and simulating the design
  1. Run Active VHDL by clicking on the icon on the desktop. If a window pops up regarding evaluation terms, click on "I Agree"
  2. Create a new design and store in in C:\temp
  3. Select "Add existing resource files" if you have already typed up your vhdl, otherwise select "Create new source files now"
  4. Once you have gotten you files loaded and compiled into Active VHDL, select Simulation->Initialize Simulation. (If you do not remember how to load and compile files go back to the Aldec tutorial)
  5. Click on the small button next to the save icon to create a new waveform.
  6. Select "Waveform->Add Signals" and add all the signals in your testbench.
  7. Push the "Run" button and see if the output is what you hoped it would be.
  8. If the design works correctly, demonstrate it to your TA.
  9. Copy your files to your network drive or a disk and remove them from the local machine so that other people cannot copy them.
  10. E-mail your lab report, design vhdl file, and testbench vhdl file to your TA.