Homework 2
UCR EE/CS120B: Introduction to Embedded Systems
Spring Quarter 2002, Prof. Frank Vahid
Due April 18 before lecture


1. Design a 3-bit register implementing the following specifications:
     Inputs:   I2, I1, I0, clk, S1, and S0
     Outputs:  O2, O1, O0
     Function: S1 S0 = 0  0 -- maintain current value
                     = 0  1 -- load I as new current value
                     = 1  0 -- Shift current value left, shifting in a 0
                     = 1  1 -- clear current value to 0
               The O signals should always output the current value. 
     Guidelines: Use 3 D flip-flops, multiplexors, and minimal additional
                 logic.
                 The clk input should be input directly to all flip-flops
                 without going through any logic. 

2. Redesign the above register so that it has the following inputs:
     I2, I1, I0, clk, load, lshift, clear
   The meaning of the last three signals should be obvious. If two or
   three of those signals are asserted in the same clock cycle, the 
   register should simply maintain its current state.

3. (a) Design a 4-bit counter implementing the following specifications:
     Inputs:   I3, I2, I1, I0, clk, inc
     Outputs:  TC, O3, O2, O1, O0
     Function: inc = 1 -- add 1 (roll over to 0000 if at 1111)
               The O signals should output the current value. 
               The TC signal should be 1 for one cycle if inc=1 and we 
                  reach 1111
     Guidelines: Use 4 D flip-flops, multiplexors, and minimal additional
                logic. The clk input should be input directly to flip-flops.
   (b) Show how to cascade two such counters to create an 8-bit counter. 

4. ESD 2.13

5. Design a circuit with the following specifications:
     Inputs:   I (16 bits wide), clk, start
     Outputs:  Sum, Avg, Min, Max
     Function: When start becomes 1, begin observing the values on
               I on each rising clock edge. Maintain the sum, average,
	       minimum and maximum values (since start became 1) on the 
	       corresponding outputs. When start falls to 0, just hold
	       the outputs with their previous value (but these values
	       will be reset next time start becomes 1). 
     Guidelines: Start with an FSMD, then draw an FSM plus a structural
               datapath, then implement the FSM as a controller, but using
	       a ROM as the combinational logic. So your final design
	       should include both the controller and the datapath,
	       with all connections clearly shown and labeled.

6. Design a circuit that computes n! (n factorial): 
     Inputs:   N (16 bits wide), clk
     Outputs:  R 
     Function: R = N! 
     Guidelines: Start with a C algorithm, convert it to an FSMD (do
               not simplify the FSMD initially), simplify the FSMD,
	       split the FSMD into an FSM and a datapath. You need not
	       implement the FSM. Notice that R will not always properly
	       reflect N! as it takes some time to compute N! for a
	       new N -- clearly indicate the number of cycles that your
	       circuit will require to compute N! in the worst possible
	       case.