-- Shawn Nematbakhsh
-- UNIX DES Password Cracker 
-- Global entity

library IEEE;
use IEEE.STD_LOGIC_1164.all; 
use IEEE.STD_LOGIC_ARITH.all;

entity global is
	port(
		clk: in std_logic;
		rstt: in std_logic;
		ACK: in std_logic;

		D: out std_logic;
		light: out std_logic;
		REC: out std_logic);
end global;

architecture bhv of global is	


constant a   : UNSIGNED (6 downto 0) := "1100001"; 
constant z   : UNSIGNED (6 downto 0) := "1111010";


type STATE is (BEG,DELAY1,DELAY2,FEED,WAITING,CHECKS,STALLS);
signal exe_state : STATE;

signal data_shift: std_logic_vector(63 downto 0);
signal j: UNSIGNED(3 downto 0);
constant C0_56    : std_logic_vector (63 downto 0) := "0000000000000000000000000000000000000000000000000000000000000000";


signal v: UNSIGNED(6 downto 0);



--------------------------------------------------------
-- Key permutation, converts a 64 bit key into a 56 bit key, ignoring parity
function des_kp(din   :std_logic_vector (63 downto 0))
return std_logic_vector is
variable val 	:std_logic_vector (55 downto 0);
  begin
    val := din(64-57) & din(64-49) & din(64-41) & din(64-33) & din(64-25) & din(64-17) & din(64- 9) & din(64- 1) &
           din(64-58) & din(64-50) & din(64-42) & din(64-34) & din(64-26) & din(64-18) & din(64-10) & din(64- 2) &
           din(64-59) & din(64-51) & din(64-43) & din(64-35) & din(64-27) & din(64-19) & din(64-11) & din(64- 3) &
           din(64-60) & din(64-52) & din(64-44) & din(64-36) &

           din(64-63) & din(64-55) & din(64-47) & din(64-39) & din(64-31) & din(64-23) & din(64-15) & din(64- 7) &
           din(64-62) & din(64-54) & din(64-46) & din(64-38) & din(64-30) & din(64-22) & din(64-14) & din(64- 6) &
           din(64-61) & din(64-53) & din(64-45) & din(64-37) & din(64-29) & din(64-21) & din(64-13) & din(64- 5) &
           
           din(64-28) & din(64-20) & din(64-12) & din(64- 4);
    return val;
  end des_kp;

-- increments character string for brute force search  
function inc(s : UNSIGNED(63 downto 0))
return UNSIGNED is
variable state : UNSIGNED(63 downto 0);
  
  begin			
            -- cycle through lowercase chars for brute force search  
	  		state := s;
	  		if(state(63 downto 57) = z) then
					state(63 downto 57) := a;	   
					if(state(55 downto 49)=z) then
						state(55 downto 49):=a;
						if(state(47 downto 41)=z) then
							state (47 downto 41):=a;						 
							if(state(39 downto 33)=z) then
								state(39 downto 33):=a;
								if(state(31 downto 25)=z) then
									state(31 downto 25):=a;
									if(state(23 downto 17)=z)  then
										state(23 downto 17):=a;
										if(state(15 downto 9)=z) then
											state(15 downto 9):=a;						   
											if(state(7 downto 1)=z) then
												state(7 downto 1):=a;
											else
												state(7 downto 1) := state(7 downto 1) + '1';
											end if;
										else
											state(15 downto 9) := state(15 downto 9) + '1';
										end if;
									else
										state(23 downto 17) := state(23 downto 17) + '1'; 
									end if;
									
								else
									state(31 downto 25) := state(31 downto 25) + '1'; 
								end if;
							else
								state(39 downto 33) := state(39 downto 33) + '1';
							end if;
						else
							state(47 downto 41) := state(47 downto 41) + '1';
						end if;
					else
						state(55 downto 49) := state(55 downto 49) + '1';
					end if;	
				else
					state(63 downto 57) := state(63 downto 57) + '1';
				end if;			  
				
		return state;
end inc;
  

component keygen is	 
	port(
		clk: in std_logic;
		rst: in std_logic;
		enable: in std_logic;
		keyout: out std_logic_vector(63 downto 0));
		
		
end component;
  
  

component LCD is
	port( 
		clk: in std_logic;
		rst: in std_logic;
   	    ASCII: in std_logic_vector(63 downto 0);		   
		ACK: in std_logic;
		rdy: in std_logic;
		D: out std_logic;
		REC: out std_logic);
		
		
		
end component;

component div is
	port( 
		clk: in std_logic;
		rst: in std_logic;
		   
		clk_out: out std_logic);
		
end component;

component des_fast
    port (clk		:in std_logic;
          reset		:in std_logic;
          stall		:in std_logic;	   
		  salt      :in std_logic_vector(11 downto 0);

	  	  encrypt	:in std_logic;  -- 1=encrypt, 0=decrypt
          key_in	:in std_logic_vector (55 downto 0);
          din		:in std_logic_vector (63 downto 0);
          din_valid     :in std_logic;

          dout		:out std_logic_vector (63 downto 0);
          dout_valid	:out std_logic;
          key_out	:out std_logic_vector (55 downto 0)
         );
end component;


	signal s: UNSIGNED(63 downto 0);	  
	signal clk_out: std_logic;
	signal rdy: std_logic;
	signal ASCII: std_logic_vector(63 downto 0);
    signal din: std_logic_vector(63 downto 0);
	signal din_valid: std_logic;
	signal stall: std_logic;
	signal dout: std_logic_vector(63 downto 0);
	signal dout_valid: std_logic;		 
	signal key_in: std_logic_vector(55 downto 0);
	signal salt: std_logic_vector(11 downto 0);	 
	signal key_out : std_logic_vector(55 downto 0);		   
	signal stage : UNSIGNED(4 downto 0);
	signal passes: UNSIGNED(4 downto 0);   
	signal valid_data: std_logic; 
	signal target: std_logic_vector(63 downto 0);


begin
	
	DIV1: div port map(clk,rstt,clk_out);
	LCD1: LCD port map(clk_out,rstt,ASCII,ACK,rdy,D,REC);
	DES1: des_fast port map(clk_out2,rstt,stall,salt,'1',key_in,din,din_valid,dout,dout_valid,key_out);

process(clk_out,rstt)
	begin
		if(rstt = '1') then		
			-- target hash
		    target <= "0001011110011010101010101011101011011110001111100101011110011101";
			valid_data <= '0';
			s <= a & '0' & a & '0' & a & '0' & a & '0' & a & '0' & a & '0' & a & '0' & a & '0';
			stage <= "00000";
			salt <= "001001001001";
			din_valid <= '0';
			light <= '1';
			rdy <= '0';
			ASCII <= "0100100101010100010101110100111101010010010010110101101001011010";
			passes <= conv_unsigned(0,5);	  
			din <= "0000000000000000000000000000000000000000000000000000000000000000";	   
			exe_state <= BEG;
			salt <= "001001001001";
			stall <= '0';
			key_in <= des_kp(std_logic_vector(s));
			
		elsif(clk_out'event and clk_out='1') then
			

			case exe_state is
				
				when BEG =>
					s <= inc(s);  
					exe_state <= FEED;
				
				when FEED =>   
					
					din_valid <= '1';
					stage <= stage + '1';	  
					key_in <= des_kp(std_logic_vector(s));
					s <= inc(s);
				
	
					if(stage = conv_unsigned(15,4)) then	   
					
						exe_state <= DELAY1;   
		
					else
							    
						exe_state <= FEED;
				
					end if;		 
				    
					din <= "0000000000000000000000000000000000000000000000000000000000000000";
			
				when DELAY1 =>
					
					exe_state <= WAITING;	
					din_valid <= '0';	
					stage <= "00000";
		
				when WAITING =>
							  
					din_valid <= '1';
					key_in <= key_out;
					stage <= stage + '1';
					din <= dout;
				
					if(stage = conv_unsigned(16,5)) then  
					
						passes <= passes + '1';	  
						stage <= "00000";
						exe_state <= DELAY2;
						
					end if;
							   
				
				when DELAY2 =>			
				din_valid <= '0';		
				key_in <= key_out;
				if(passes = conv_unsigned(24,5)) then	 
				

					stage <= "00000";
				
						

					exe_state <= CHECKS;
							
				else
					exe_state <= WAITING; 
				end if;
				
				when CHECKS =>	   
				
				    -- found match? display result and loop forever
					if(dout = target) then	
						ASCII <= "0100100101010100010101110100111101010010010010110101101001011010";
						light <= '0';
						rdy <= '1';
						exe_state <= STALLS;		   
					
					elsif(stage = 15) then
						
						ASCII <= "0100100101010100010101110100111101010010010010110101101001011010";
				     	light <= '0';
						rdy <= '1';	  
			
						passes <= conv_unsigned(0,5);  
						din <= "0000000000000000000000000000000000000000000000000000000000000000";
						stage <= "00000";
	
						exe_state <= FEED;	   
				  
					else
						stage <= stage + '1';
					
					end if;	 
			--	when STALLS =>

					


					--	rdy <= '1';
					--light <= '0';
				--	exe_state <= STALLS;

			    when others =>
			end case;
		end if;
			
			
--		if(rdy = '1') then
--				rdy <= '1';
--				light <= '1';
--		end if;

--		if(din_valid = '0' and dout_valid = '0') then
--				din_valid <= '1';
--				passes <= passes + '1';
--				light <= '1';
		
--			elsif(dout_valid = '1') then
--					light <= '1';
--					if(passes < conv_unsigned(25,5)) then
--						din_valid <= '1';
--						din <= dout;				 
--						passes <= passes + '1';
					--	key_in <= "11100011110101110111111011111110110110111111010001101101"; -- password quovohm
--					else
--			    		rdy <= '1';
--						if(dout = "1100101111011111000100010100111010100000010111001010110011010110") then
--							ASCII <= "0100100101010100010101110100111101010010010010110101101001011010";
--						else
--							ASCII <= "0101010101010011010101010101100001001111010100100101101001011010";
--						end if;
--				 	end if;
		--	elsif(busy='1') then
		--		din_valid <= '0';
	
--			end if;
--		 end if;
	  end process;
end bhv;