---------------------------------------------------------------------------------------------------
--
-- Title       : Test Bench for spinner
-- Design      : spin
-- Author      : ucr
-- Company     : ucr
--
---------------------------------------------------------------------------------------------------
--
-- File        : $DSN\src\TestBench\spinner_TB.vhd
-- Generated   : 8/20/2004, 7:40 PM
-- From        : $DSN\src\spinner.vhd
-- By          : Active-HDL Built-in Test Bench Generator ver. 1.2s
--
---------------------------------------------------------------------------------------------------
--
-- Description : Automatically generated Test Bench for spinner_tb
--
---------------------------------------------------------------------------------------------------

library ieee;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_1164.all;

	-- Add your library and packages declaration here ...

entity spinner_tb is
end spinner_tb;

architecture TB_ARCHITECTURE of spinner_tb is
	-- Component declaration of the tested unit
	component spinner
	port(
		clk : in std_logic;
		rst : in std_logic;
		start : in std_logic;
		outclock : out std_logic;
		finished : out std_logic );
	end component;

	-- Stimulus signals - signals mapped to the input and inout ports of tested entity
	signal clk : std_logic;
	signal rst : std_logic;
	signal start : std_logic;
	-- Observed signals - signals mapped to the output ports of tested entity
	signal outclock : std_logic;
	signal finished : std_logic;

	-- Add your code here ...

begin

	-- Unit Under Test port map
	UUT : spinner
		port map (
			clk => clk,
			rst => rst,
			start => start,
			outclock => outclock,
			finished => finished
		);
	clock: process
	begin
		clk <='1';
		wait for 1 ns;
		clk <='0';
		wait for 1 ns;
	end process clock;	
	
	test: process
	begin
		rst  <='1';start <='0';
		wait for 40 ns;
		rst  <= '0';
		wait for 50 ns;
		start <='1';
		wait for 10 ns;
		start <='0';
		wait for 500 ns;
	end process test;
end TB_ARCHITECTURE;