Home | NODES | Contact Info

Brief Resume

      I will be glad to provide you with a detailed resume together with a list of references if interested. Drop a note

EDUCATION:
MS in CSE, UCR (Expected Graduation March 2005) 3.86/4.00 (fellowship for the full period of studies)
B.Tech in EE, IIT Kharagpur, India (2003), 8.45/10.00 (scholarship for the full period of studies)

MASTERS PROJECT:(Advisor: Prof Walid Najjar)
    Conceptualized and Developed under the guidance of advisor, Dr. Najjar, design of an embedded sensor device around the Chipcon CC1010 SOC. The design has the potential for a paradigm shift in the development of wireless embedded sensors, leading to multipronged improvements including, but not limited to these disciplines:

  • Hardware - Software development for embedded systems.
  • Communication / networking protocols for sensor and ad-hoc networks.
  • File / Database management for sensor systems.


    • This research effort now brings together the people working in different areas of sensor networks in our department under a single umbrella called the NODES project.
    We now meet biweekly to bounce ideas off each other.

    Publications
    [1]S. Neema, A. Mitra, A. Banerjee, W. Najjar, D. Zeinalipour-Yazti, D. Gunopulos, V. Kalogeraki, “NODES: A Novel System Design for Embedded Sensor Systems”, submitted to The Fourth International Conference on Information Processing in Sensor Networks (IPSN'05), Special track on Platform Tools and Design Methods for Network Embedded Sensors (SPOTS), 2005
    [2] D. Zeinalipour-Yazti, S. Neema, D. Gunopulos, W. Najjar, V. Kalogeraki, “Data Acquisition in Sensor Networks with Large Memories”, accepted for publication 1st IEEE International Workshop on Networking Meets Databases,(NetDB), 2005

    INTERNSHIP EXPERIENCE
    Intern at NEC-LABS , Princeton NJ. Intern in the System LSI Division. Development of H.263 encoder in NEC-BDL (behavioral description language) and to integrate it into the existing HW and SW design flows enabling efficient HW/SW partioning.

    RELEVANT LANGUAGE SKILLS:
    C++ (strong): number of projects, most recent project: Back End of Compiler for C-Minor
    VHDL(strong): 3 quarters of Instructing and debugging experience as TA plus projects
    Perl(strong): scripting use for current MS project
    microcontroller C/NesC (strong): current MS project
    SystemC (familiar): As part of coursework
    Verilog(familiar): Project as undergrad

    TOOLS:
    Xilinx ISE, Triscend fastchip, Aldec ActiveHDL, ModelSim, Cadence Analog Artist, gdb

    RELEVANT COURSEWORK:
    Advanced Embedded and Real Time Systems (A+)
    Synthesis and Optimization of Digital Circuits (A+)
    Advanced Computer Architecture (A)
    Compiler Construction (A)
    Advanced Computer Networks (A)