ROCCC Web Site


	RIVERSIDE OPTIMIZING COMPILER FOR CONFIGURABLE COMPUTING


PUBLICATIONS	PEOPLE	ROCCC Web Compiler(Temporarily Disabled)

ROCCC Synopsis ROCCC is a C to hardware compilation project whose objective is the FPGA-based acceleration of frequently executed code segments (loop nests). It focus is on extensive compile-time transformations and optimizations with the aim of: Maximizing parallelism by exploiting functional, loop and operation parallelism. Maximizing the troughput of a computation. Minimizing the number of off-FPGA memory accesses. Minimizing the area occupied by the circuit. In its current version, ROCCC is built using the SUIF2 framework with MachSUIF. In the process of deveoping ROCCC we have evolved the SUIF toolset into NuSUIF. ROCCC relies on a novel intermediate representation: CIRRF (Compiler Intermediate Representation for Reconfigurable Computing). ROCCC has received past support from DARPA (ACS), NSF and LANL (through the CARE Program). It is currently supported by Xilinx and IBM.

NuSUIF Synopsis The ROCCC compiler is built using SUIF 2. In building ROCCC we have updated and improved many features of the SUIF toolset, including a new front-end based on gcc 4.0.

CIRRF Synopsis Configurable computing relies on the expression of a computation as a circuit. Its main purpose is the hardware based acceleration of programs. This computation model has received renewed interest with the recent rapid increase in both size and speed of FPGAs. One of the major obstacles in the way of wider adoption of (re)configurable computing is the lack of high-level tools that support the efficient mapping of programs expressed in high-level languages (HLL) to reconfigurable fabrics. The major difficulty in such a mapping is the translation from a temporal execution model to a spatial execution model. An intermediate representation (IR) is the central structure around which tools such as compilers and synthesis tools are built. We propose an IR specifically designed for reconfigurable fabrics: CIRRF (Compiler Intermediate Representation for Reconfigurable Fabrics). We describe the design of CIRRF and its initial implementation as part of the ROCCC compiler for translating C code to VHDL. CIRRF is designed to support the creation of a data path and the scheduling of operations on it. It provides support for buffers, look-up tables, predication and pipelining in the data path. One of the important features of CIRRF, and ROCCC, is its support for the import of pre-designed IP cores into the original C source code allowing the user to leverage the huge wealth of existing IP cores while programming the configurable platform using a HLL. We have extended CIRRF to support partial run-time reconfiguration on the FPGA. Using experiments and examples we show that CIRRF is a solid foundation to generate high-performance hardware.

PUBLICATIONS A. Mitra, Z. Guo, A. Banerjee, W. Najjar. Dynamic Co-Processor Architecture for Software Acceleration on CSoCs, IEEE Int. Conf. on Computer Design (ICCD 2006), San Jose, CA, October 2006. Z. Guo, A. Mitra and W. Najjar. Automation of IP Core Interface Generation for Reconfigurable Computing, in 16th International Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, August 2006. Z. Guo and W. Najjar. A Compiler Intermediate Representation for Reconfigurable Fabrics, in 16th International Conference on Field Programmable Logic and Applications (FPL 2006), Madrid, Spain, August 2006. D. Suresh, Z. Guo, W. Najjar. Automatic compilation framework for Bloom filter based intrusion detection, Int. Workshop On Applied Reconfigurable Computing (ARC 2006)  Delft, The Netherlands, March 1-3, 2006. B. A. Buyukkurt, Z. Guo, W. Najjar. Impact of Loop Unrolling on Throughput, Area and Clock Frequency in ROCCC: C to VHDL Compiler for FPGAs, Int. Workshop On Applied Reconfigurable Computing (ARC 2006)  Delft, The Netherlands, March 1-3, 2006. D. Kulkarni, W. Najjar, R. Rinker, F. Kurdahi. Compile-time Area Estimation for LUT-based FPGAs. In ACM Trans. on Design Automation of Electronic Systems, January 2006. Z. Guo, B. Buyukkurt, W. Najjar and K. Vissers. Optimized Generation of Data-Path from C Codes. In ACM/IEEE Design Automation and Test Europe (DATE), Munich, Germany, March 2005. G. Stitt, Z. Guo, F. Vahid, and W. Najjar. Techniques for Synthesizing Binaries to an Advanced Register/Memory Structure. ACM/SIGDA Symp. on Field Programmable Gate Arrays (FPGA), Feb. 2005. Z. Guo, A. B. Buyukkurt and W. Najjar. Input Data Reuse In Compiling Window Operations Onto Reconfigurable Hardware, Proc. ACM Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES 2004), Washington DC, June 2004. Z. Guo, W. Najjar, F. Vahid and K. Vissers. A Quantitative Analysis of the Speedup Factors of FPGAs over Processors, In. Symp. on Field-Programmable gate Arrays (FPGA), Monterrey, CA, February 2004. W. Najjar, W. Böhm, B. Draper, J. Hammes, R. Rinker, R. Beveridge, M. Chawathe and C. Ross. From Algorithms to Hardware – A High-Level Language Abstraction for Reconfigurable Computing. IEEE Computer, August 2003. D. C. Suresh, W. A. Najjar J. Villareal, G. Stitt and F. Vahid. Profiling Tools for Hardware/Software Partitioning of Embedded Applications. Proc. ACM Symp. On Languages, Compilers and Tools for Embedded Systems (LCTES 2003), San Diego, CA, June 2003. Z. Guo, D. C. Suresh, W. A. Najjar. Programmability and Efficiency in Reconfigurable Computer Systems, Workshop on Software Support for Reconfigurable Systems, held in conjunction with the Int. Conf. Of High-Performance Computer Architecture, Anaheim, CA, February 2003.

PEOPLE Ayse Betul Buyukkurt Zhi Guo Abhishek Mitra John Cortes Jason Villareal Julien Jacques