Workshop on
Tools and Compilers for Hardware Acceleration (TCHA)
September 17, 2006
Seattle,
Washington
in conjunction with
PACT 2006
" ... hardware acceleration
is the use of hardware to perform some function faster than is possible
in software running on the normal (general purpose) CPU." (from
Wikipedia, The Free Encyclopedia).
Accelerators range from CPU multimedia extensions, to GPUs, multicore
SOCs and FPGAs. Applications range from high-performance computing, to
graphics and gaming.
The objective of TCHA is to bring together researchers and
practicioners of hardware based code acceleration fromvarious
backgrounds and interests.
Topics of interest include, but are not limited to:
- Static and dynamic compilation techniques
- Language extensions
- Relationship to emerging multi-core techniques
- Programming models
- Performance tools
Important dates and
deadlines
- Submission: August 1st, 2006, 11:59PM PDT
- Acceptance: August 12th, 2006
- Final version: August 26th, 2006
Program committee
Walid Najjar (chair), UC Riverside
Kathryn O'Brien (co-chair), IBM
Wim Böhm, Colorado State University
Pradeep Dubey, Intel
Maya Gokhale, Los Alamos Natonal Lab
Xavier Martorell, UPC Barcelona
Michael McCool, RapidMinds
Bilha Mendelson, IBM
Santosh Pande, Georgia Institute of Technology
Dan Poznanovic, SRC
Christophe Wolinski, U. de Rennes
Submission guidelines
Submissions should be extended abstracts or position papers
of 2-4 pages,
double-column, in 11-point font. Include the list
of authors and their affiliations, addresses, telephone and fax
numbers, email addresses and the name of the corresponding
author. Please send submissions by the deadline
via email to Walid Najjar at najjar@cs.ucr.edu or Kathryn O'Brien at kmob@us.ibm.com.