Workshop on
Tools and Compilers for Hardware Acceleration (TCHA)

September 17, 2006
Seattle, Washington
in conjunction with PACT 2006

PROGRAM

PROCEEDINGS

8:30 Session 1:

Intermediate Representation for HLL Programmable Logic Compilers    [presentation]

Maya B. Gokhale, Justin L Tripp, Kristopher D. Peterson (Los Alamos National Laboratory)

Integrating User HDL during MAP C and Fortran Compilation     [presentation]

Jeffrey Hammes (SRC Computers, Inc)

Acceleration of Dynamic Programming Codes Using ROCC   [presentation]

Betul Buyukkurt, Walid A Najjar (University of California Riverside)

Performance Estimation for FPGA Acceleration

Prasanna Sundararajan, Dave Bennet, Jeff Mason (Xilinx Inc)

10:30 Break

11:30 Session 2:

Compiling for Increasing On-chip parallelism

Yuan Zhao, Ken Kennedy (Rice University)

Data Management in the Cell OpenMP Compiler

Kevin O’Brien,Kathryn O’Brien, Zehra Sura, Tong Chen  (IBM Research)

Autoscoping Support for OpenMP Compiler

Laksono Adhianto, Barbara Chapman (University of Houston)

12:30 - 1:30 Lunch

1:30 Session 3:

Tools for Compiling to Coarse Grained Reconfigurable Arrays  [presentation]

Carl Ebeling (University of Washington)

Program Analysis Tools for Application Specific Architectures   [presentation]

Maya B. Gokhale, Matthew J Sottile (Los Alamos National Labs)

03:00 Break

3:30 Session 4:

Performance Evaluation of the Altera C2H Compiler on Image Processing Benchmarks  [presentation]

Daniel Etiemble*, Stephane Piskorski*, Lionel Lacassagne** (*LRI, ** IEF,University of Paris Sud)

Implementing Scientific Applications Hybrid HPC Systems  [presentation]

Daniel Chavarria-Miranda, Andres Marquez (Pacific Northwest National Laboratory)

Impact of Multi-Core Memory Architecture on CFD Simulations for Feature Film Visual Effects

Yahya H Mirza (Aurora Borealis Software LLC)

Discussion and Concluding Remarks