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Manuel Minwary

(sorry for the lousy pic, its the only one i can find in my messy comp HD T_T)

Interest- Embedded System, IC designing, Home Improvement, and playing way too much Games

Design Project in Architecture / Embedded Systems

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Week 1
Date	Hours	Summary	Ideas/Issues/Plans		Links/Documents
Mon, Mar 29	-
Tue, Mar 30	-
Wed, Mar 31	2	Created this BLOG	Been a year since ive taken the cs120A/B series so I reviewed old materials from those classes.
Thu, Apr 1	3	Found some interesting websites about the basic of FPGA Research some of the tradeoff for paper on next disc
Fri, Apr 2	2	Research jpeg compression	Fromt he looks of it JPEG project is a nightmare. Theres 3 steps 1.Huffman decoding 2.Quantizer 3.IDCT Even if we find an example code of how to decompress jpeg it will be hard to reverse engineer it to meet our demands. It seems for the JPEG decoder project we would need more time. In addition we have to figure out a way to input data from storage medium, plus figure out a way to output via VGA		VHDL JPEG decoder
Sat, Apr 3
Sun, Apr 4	2	More jpeg research, esp into the vga and storage input part	The Xilinx board has a vga port output, convenient but still we have to write a code for the output signal to be VGA spec. Looking at a few sites about VGA output signal, the process will be hard to do on the xilinx board, this is a big problem. From what i gathered memory will be another big problem that will need solving. Would the Xilinx chip have enough memory to contain the decompresed JPEG file? Because bitmap file are quite big, memory wise.		VGA output VGA signal spec
Week 2
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, Apr 5	3	Research FPGA some more		Learning that the JPEG project is a nightmare I decided to reseearch FPGA some more to see if its better suited for our team. FPGA has few basic component this include the CLB, Switch Matrix, and I/O. Each person in our group should be able to write for each component, might be able to finish the project faster this way. The CLB architecture looks like its prety straightforward, not too hard to implement in vhdl, same goes for I/O, but the switch matrix looks a little tricky to implement in VHDL. Seems like the FPGA project would be alot better than the JPEG one in term of having enough time to complete it		CLB FPGA in general FPGA in detail
Tue, Apr 6	3	Research all the different types of FPGA from the different companies that makes them. Wrote the Tradeoff analysis		Looks like all FPGA can be divided into 3 groups based on what kind of CLB it uses, fine, medium or coarse grain. Most modern FPGA has tens and thousand of CLBs, writing each component in VHDL seems easy enough, but I am very worried when we have to connect these components together. With maybe thousands of components to be connected together, the process will take a while, and there will be alot of chances that we connect it wrong.		Tradeoff
Wed, Apr 7	2	Class meet. Found out that my partners decided to do the JPEG instead. Back to researching JPEG for the proposal paper.		Mostly worried about the time isssue on the JPEG project, seems like time to prototype will be far off than projected. Greg suggest for us to use codes on the internet and modify it to suit our needs. Using a storage medium like compact flash to store JPEG to decode will force us to use some of our time to learn their I/O interface, using up more time that we may not have.
Thu, Apr 8	2	Still trying to find good codes from the web.		All the codes that ive run across are very cryptic, very hard to understand pass the huffman decoding.
Fri, Apr 9
Sat, Apr 10
Sun, Apr 11
Week 3
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, Apr 12	2	Read the previous course page of cs122b		Alot of info from 122b page, it has very good links on the basic of FPGA. Started reading the intro of FPGA and PLD
Tue, Apr 13	2	Read more of previous course page Group meet online Worked on project proposal		Finish reading the intro to fpga on the previous course page, I understand the overall picture of how FPGA work now. All of us worked and finish the project proposal. We partition the proposal into the different sections and each person did it.		Proposal
Wed, Apr 14
Thu, Apr 15	3	planned out what to implement first and who will do what.		we divided group into 2 subgroup, me and Dennis will do the VHDL implementation, Khuyen and Roberto will do the C++ implementation of the FPGA. While the VHDL implementation is prety clear on how to do, we are still unsure of how to do the implementation in C++ with SimpleScalar. We will have to research harder on SimpleScalar.
Fri, Apr 16
Sat, Apr 17	1	Khuyen points out the vahid previous course page has good info on SimpleScalar, hopefully he now knows enough to get the C++ implementation started
Sun, Apr 18
Week 4
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, Apr 19	3	Today I was mostly concerned of reading and doing homework from the Art of Designing Embedded System book.		Read a couple of chapters from the book so far. The book is very interesting and gives alot of information about engineering in a real world view. The second chapter of the book made me realize that I need to improve on alot of the things I do when doing a project/program. I finish most of the HW problems except the last 3. Will finish before wed this week.
Tue, Apr 20	2	Finish reading the necesarry chp of the book, and finish the HW.		read some more of the book and try to review and browse over previous chapters for the upcoming quiz, hopefully it will not be too hard. Also i finish last 3 questions of the homework. I found chapter 3 of the book is extremely informational, I shall never try to write big program anymore. I couldnt find a good picture of myself readily available in my comp for homework question 12 and my sister have my digital camera with her. I will post a better picture in a couple of week when shes back.
Wed, Apr 21	2	Planned a schedule of this weekend.		Me and Dennis shall meet Friday and all weekend to get the first prototype done.
Thu, Apr 22
Fri, Apr 23	2	Meet up in Surge and started working on my part of the project, the VHDL part.		Me and Dennis got the over all skeleton of the CLB coded. The datapath of the CLB is overall complete but the components inside it like the LUT is still not coded yet, we will come back tomorow and work on it some more.		FPGA were doing
Sat, Apr 24	4	Meet up again in Surge and worked on in some more, the goal for today was to get the CLB and start the simulation of it.		Me and Khuyen worked on the individual component of the CLB. For the LUT we decide instead of using individual SRAM blocks that connects to a big MUX we will use a simple 8x2 register since both work exactly the same but register is much easier to manage.		CLB basics
Sun, Apr 25	4	Another big and long day today. We finished the CLB in VHDL and now we are writing the testbench for it.		We worked on the testbench. the first one we wrote was only a simple logic function that computest the following equation F=A'B+AC. The testbench worked and output the correct answer. Next we made a more complicated testbench but we ran into a major error. I thought we can make a 3bit adder from the 2 LUT since each LUT can input 3 bits and the output of the 2 is 4bits. After writing a 1k line testbench and trying to simulate it, I suddenly realize that my logic is wrong and that 3bits adder cannot be done. After a few min thinking about the problem, we found out that we can do a 2bit ripple adder instead, so i modify my code and do the testbench for a 2bit ripple adder.		copy paste component
Week 5
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, Apr 26	1	Meet up to discuss the presentation on wednesday.		We divided up the presentations into 4 parts for the 4 people in our group
Tue, Apr 27
Wed, Apr 28	2	Did the presentation. Realize from another team presentation that the input can be a bitstream like real FPGA if we use shift registers, and having two clock would be very useful, one that programs the LUT and one is user clock.		I will have to change the register in our CLB to a shift register this weekend when our team meets again.		shift register
Thu, Apr 29
Fri, Apr 30		Read up on switch matrix.		I think i got the basic idea of it now to start coding the switch matrix. Hopefuly Roberto and another teammember can get started on the SimpleScalar part of our project
Sat, May 1
Sun, May 2
Week 6
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, May 3
Tue, May 4
Wed, May 5
Thu, May 6
Fri, May 7
Sat, May 8
Sun, May 9
Week 7
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, May 10
Tue, May 11
Wed, May 12
Thu, May 13
Fri, May 14
Sat, May 15	2	Try to connect the CLB to the SM		The connections between the CLB and SM is very complicated and tedious because any wire from the CLB can connect to any 4 sides of the switch matrix The progress is currently very slow, there is so much connections to check and recheck to make sure its correct.
Sun, May 16	2	Still working on CLB to SM connections		Same as yesterday slow progress
Week 8
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, May 17	2	Got bored with connections, start reading the 7 habits book for Wed		Book is very interesting up to the part I am reading now, I can kinda tell why companies would want their employees to read this book.
Tue, May 18	2	Read up some more of the 7 habits book
Wed, May 19	1	Discuss with teamates after class as to our goal for the final prototype		We hope to have a full functional 2x2 CLB FPGA at the least for the final prototype that can take in a bitstream to configure it.
Thu, May 20	2	Still working on CLB to SM connections		Progress is slow but progress nonetheless
Fri, May 21
Sat, May 22
Sun, May 23	2	Still............. working on CLB to SM connections		Taking more time than anticipated, but i should be able to get it done in another day.
Week 9
Date	Hours	Summary		Ideas/Issues/Plans		Links/Documents
Mon, May 24	4	Done with the CLB to SM connector....finaly Moving on to simulation to check if everything works correctly		After many days of connecting the CLB and SM its finaly done, there are so many connections! On top of that the bitstreaming to program the connections between the two is a nightmare, never ever want to do it again. After I last counted there are 320 bits of shift register just to program the the connections between the CLB and SM, this is not counting the bitstream to program the SM itself and CLB itself.
Tue, May 25	2	T_T just tested the CLB to SM connector and its not working as it should, debuging.		Debuging took me quite some time to figure out that one of the component is not working as intended. It seems that when one connect merge multiple datapath to one, the unsigned signal will always overmask everything.\ I need to figure out a way to get around this to make the component work with the others.
Wed, May 26	2	Class discussion. Debug some more, its taking longer that expected.		Talk with other team members as to what is our final prototype goals. Hopefully we can stamp everything out by this weekend, and leave Monday and Tuesday for making our presentation and report.
Thu, May 27
Fri, May 28
Sat, May 29