What's all the "Buzz" about SystemVerilog?
What is SystemVerilog?    |    Analysis    |    Technical Documents  |     Publications / Articles  

Assignment: " Try to find some good publications that summarize its [SystemVerilog] features and technical details. We may even want to capture some designs using it in the future. "

 

What is System Verilog

Emerging fast as a possible IEEE standard, SystemVerilog seeks to extend Verilog-2001 by adding "C++-like" constructs and assertion-based verification to the standard Verilog language. Instead of using higher-level data structures provided by C/C++ in a Verilog verification environment (Verilog Programming Language Interface a.k.a PLI), SystemVerilog seeks to allow a single development environment for those who design hardware at the system level and those who design hardware at the implementation level.

     From the SystemVerilog Language Reference Manual(LRM):
"SystemVerilog 3.0 is built on top of Verilog 2001. SystemVerilog improves the productivity, readability, andreusability of Verilog based code. The language enhancements in SystemVerilog provide more concise hard-waredescriptions, while still providing an easy route with existing tools into current hardware implementationflows. SystemVerilog adds several new constructs to Verilog-2001, including:"
— C data types to provide better encapsulation and compactness of code
   — int, char, typedef, struct, union, enum
— Enhancements to existing Verilog constructs, to provide tighter specifications
 — Extensions to always blocks to include linting type features
— Logic (0, 1, X, Z) and bit (0, 1) data types — Automatic/static specification on a per variable instance basis
— Procedural break, continue, return — Interfaces to encapsulate communication and facilitate "Communication Oriented" design
— Dynamic processes for modeling pipelines — A $root top level hierarchy which can have global definitions

 

   

 

 

Analysis
        In summary, the benefits of SystemVerilog are as follows: SystemVerilog is backward compatible with Verilog, SystemVerilog contains "abstraction-raising" C++-style constructs taking Verilog-2001 to the system level, and SystemVerilog boasts testbench capabilities allowing verification and design all in one environment.  Questions that have been raised about SystemVerilog include SystemVerilog is in conflict with the previous IEEE standard for Verilog, that time to standardization for a language (generally 5 years) is too slow considering Moore's Law, and that SystemVerilog is inadequate for simulation and is too small a step over Verilog-2001 for verification considering other languages such as C++ or Superlog.

Technical Documents

Article Comments
Accelera's SystemVerilog 3.0 Specification
  • Abstract: a set of extensions to the IEEE 1364-2001 Verilog Hardware Description Language to aid in the creation and verification of abstract architectural level models


  • Page 11 - Outlines SystemVerilog enhancements
DPI (Direct-C) API Donation

Supporting SystemVerilog Documents from Synopsys

 
Assertions API Donation

Supporting SystemVerilog Documents from Synopsys

 
Coverage API Donation

Supporting SystemVerilog Documents from Synopsys

 
SystemVerilog Ports & Data Types For Simple, Efficient and Enhanced HDL Modeling

 
  • Examples & comparisons between Verilog 1995, Verilog 2001, & SystemVerilog
Verilog, The Next Generation: Accellera’s SystemVerilog
  • Overview of SystemVerilog. Describes and shows syntax 24 enhancements of SystemVerilog over Verilog-2001

Some Articles About SystemVerilog

   Article Source Notable Comments/Points
1 Excerpt from SystemVerilog
Message-Board		 "Verification Guild"

  • Stu Sutherland is a member of both the SystemVerilog standards group and the IEEE 1364 Verilog standards group. He sounds off on the true intentions of SystemVerilog
2 SystemVerilog: The Next Generation Verilog Language

Accelera

  Description of  SystemVerilog Workshop to be presented @ DAC 2003
3 EDA divided on SystemVerilog
 

EE Times, Richard Goering
  • "How will SystemVerilog avoid the pitfall of trying to be one language for everybody? . . . Design and verification are different and are best done with different languages."
  • SystemVerilog 3.0, already approved by Accellera but with scant tool support, adds abstract C-like data types, enumerated types, user-defined types, interfaces, structures and other usability features . . . It adds an "assert" construct, test-bench-generation capabilities derived from Synopsys' OpenVera language, a direct C-language interface and built-in classes for verification
  • "We're trying to avoid language wars," said Stan Krolikoski, chairman of the Open SystemC Initiative. "There's a different user base for the two languages [SystemC & Verilog], although some users will have to make a decision as to which one to use."
4 'Smart' verification moves beyond SystemVerilog 3.0

 EEDesign.Com
  • This article examines donations that Synopsys is making to Accellera as a way of helping bring smart verification to SystemVerilog 3.1.

  • Article Sub-Sections:
    Smart verification
    SystemVerilog raises abstraction level
    Raising testbench productivity with higher abstraction
    Higher abstraction with assertions
    Higher level C++ modeling
    Coverage metrics drive verification closure
5 DVCon:SystemVerilog key to new design paradigm  EEDesign.Com
  • SystemVerilog 3.1 claims to bring design and verification to the assertion level, above today's Verilog and VHDL. The language, which has system level language attributes of C++ added to Verilog, allows engineers to describe a design in terms of intent or assertions. These assertions can be used by not only simulators but test bench generation and formal verification tools.

  • Synopsys also has a hand in SystemVerilog's main competition SystemC, but de Geus noted that will be used for an even higher level. SystemVerilog is an incremental step and will not require designers to make a drastic change or learn an entirely new language.
6 SystemVerilog 3.1 adds assertions and test-bench automation

EEDesign.Com
  • The June 2003 release of SystemVerilog 3.1 integrates testbench automation capabilities and temporal assertions into an enhanced version of Verilog. . . This article shows how SystemVerilog will offer a single language that can implement both design and verification