VHDL vs. SystemC

Code Comparison Sheet

Bold: Reserved Word

Italic: User_Defined Text

Task

VHDL

SystemC

Basic

Model Structure

library IEEE;

use IEEE.std_logic_1164.all;

 

entity my_model  is

                port(

                input1: in STD_LOGIC;

                input2: in STD_LOGIC; 

                output1: out STD_LOGIC;                

                output2: out STD_LOGIC;

                );

end my_model;

 

architecture my_arch of my_model is

begin

  process( input1, input2)

               variable my_var1,my_var2: STD_LOGIC;

  begin

                my_var1 :=  not input1;

                my_var2 :=  not input2;

 

                output1 <= input1 and my_var2;

              output2 <= input2 and my_var1;

 

  end process;

end my_arch;

 

#include “systemc.h”

 

SC_MODULE (my_model)

{

         sc_in<sc_logic> input1;

         sc_in<sc_logic> input2;

         sc_out<sc_logic> output1;

         sc_out<sc_logic> output2;

 

        SC_CTOR  (my_model)

         {

             SC_METHOD ( process );

             sensitive << input1 << input2;

         }

 

          void process( )

          {

                 sc_logic my_var1, my_var2;

 

                  my_var1 = ~input1;

                  my_var2 = ~input2;

   

                  output1 = input1 & my_var2;

                  output2 = input2 & my_var1;

           }

};

Logic Values

‘X’, ‘0’, ‘1’, ‘Z’

“SC_LOGIC_X” , “SC_LOGIC_0”

“SC_LOGIC_1”, “SC_LOGIC_Z”

Variable:Type Logic Bit

variable my_bit: STD_LOGIC;

sc_logic my_bit;

variable: 3-bit Logic Vector

variable my_vector: STD_LOGIC_VECTOR(2 downto 0) ;

sc_lv<3> my_vector;

Signal of Type Logic

signal my_signal: STD_LOGIC;

sc_signal<sc_logic> my_signal;

Signal for a 3-bit Logic Vector

signal my_signal: STD_LOGIC_VECTOR                                                                                                      (2 downto 0);

sc_signal<sc_lv<3> > my_signal;

Input Ports – Logic Type

input1: in STD_LOGIC;

input2,input3,input4: in STD_LOGIC;

sc_in<sc_logic> input1;

sc_in<sc_logic> input1,input2,input3;

Output Ports – Logic Type

output1: out STD_LOGIC;

output2,output3,output4: out STD_LOGIC;

sc_out<sc_logic> output1;

sc_out<sc_logic> output1,output2,output3;

Process & Sensitivity List

process( input1, input2 )

SC_METHOD ( process );

 sensitive << input1 << input2;

 

Process:

Positive

Edge- Triggered

[no predefined function-must use this code]

process(clk)

. . .

if ( clk’event and clk = ‘1’) then

. . .

SC_METHOD ( process );

 sensitive_pos  << clk;

 

Process:

Negative

Edge- Triggered

[no predefined function-must use following code]

process(clk)

. . .

if ( clk’event and clk = ‘0’) then

. . .

SC_METHOD ( process );

 sensitive_neg  << clk;

 

“Not” Input1

not input1

~input1

Input1 “AND”

Input2

…input1 and input2;

…input1 & input2;

Input1

 “OR”

Input2

…input1 or input2;

…input1 | input2;

Input1

 “XOR”

Input2

…input1 xor input2;

…input1 ^ input2;

Input1

 “NAND”

Input2

…input1 nand input2;

[no operator-must use 2 statements of code]

… input1 & input2;

… ~input;

Input1

 “NOR”

Input2

…input1 nor input2;

[no operator-must use 2 statements of code]

… input1 | input2;

… ~input;

Input1

 “XNOR”

Input2

…input1 xnor input2;

[no operator-must use 2 statements of code]

… input1 ^ input2;

… ~input;

Variable Assignment

var1 := input1 and input2;

var1 = input1 & input2;

Signal Assignment

sig1 <= input1 and input2;

sig1 = input1 & input2;

Accessing a Value From a Port

variable temp;

 

temp = input1;

sc_logic temp;

 

temp = input1.read( ) ;

Equality Operator

=

example: if ( ENABLE = ‘1’) then

==

example: if ( ENABLE == SC_LOGIC_1);

Arithmetic Operations

use IEEE.std_logic_arith.all;

…

input1 = input1 + 1;

input1 = input1  - 1;

 

[no header file for arithmetic on logic types, must convert to unsigned integer type first]

sc_uint temp;

 

temp = input1.read( ) ;

 

temp = temp + 1;

temp = temp – 1;

 

input1 = temp;

If ... Else... Structure

if(E=’1’) then

    Q = D;

    Q_P = not D;

elsif(E=’0’)then

    Q_P = D;

    Q = not D;

else

    Q = D;

    Q_P = not D;

end if;

 

if(E=’1’)

{

    Q = D;

    Q_P = ~D;

}

elsif(E=’0’)

{

    Q_P = D;

    Q = ~D;

}

else

{   Q = D; Q_P = ~D;}

Switch/Case Statement

case ctrl is

  when “0” => f <= a;

  when “1” => f <= b;

end case;

[illegal to use logic type in switch statement – must use temp variable]

 

sc_uint<2> temp = ctrl.read();

 

switch(temp)

{

                case 0: f = a; break;

                case 1: f = b; break;

}