UCRiverside Computer Science: 260 Course Description

Winter 2003
CS 260 - Advanced Topics in Computer Architecture

Instructor: Jun Yang
Time and Room: TR 12:40 -- 2:00pm, HMNSS 1502
Prerequisites: CS203A or permission of the instructor
Tentative Topics: Low power cache memories; Low power bus encoding techniques;
Embedded processor examples; Network processor examples; Thread-Level parallelism;

Course Load

Presentation Schedule

Name	Date, Day	Papers
Lan Gao	1-23-2003, Th	9, 10, 12, 13
Shaohui Chen	1-23-2003, Th	5, 6, 7
Lan Ye	1-28-2003, Tu	11, 14
Yan Luo	1-28-2003, Tu	19, 20
Banit Agrawal	1-30-2003, Th	34, 35, (32, 33)
Satya Mohanty	2-4-2003, Tu	29, 30, (36, 37)
Jia Yu	2-4-2003, Tu	1, 2, 3, 8
Ayse Betul Buyukkurt	2-6-2003, Th	21, 22
Lingling Jin	2-6-2003, Th	38, 39, 40, 42, 43
Li Zhao	2-13-2003, Th	25, 26, 27, 28
Dinesh C. Suresh	2-13-2003, Th	15, 16, 17
Zhi Guo	2-18-2003, Tu	44, 46
Yan Luo	2-18-2003, Tu	project midway presentation
Lan Ye	2-20-2003, Th	project midway presentation
Shaohui Chen	2-20-2003, Th	4, 44
Satya Mohanty	2-25-2003, Tu	29, 30
Banit Agrawal	2-25-2003, Tu	32, 33
Ayse Betul Buyukkurt	2-27-2003, Th	23, 24
Lan Gao	2-27-2003, Th	45, 47
Jia Yu	3-4-2003, Tu	Project Presentation (20min)
Lingling Jin	3-4-2003, Tu	(30min)
Dinesh C. Suresh	3-4-2003, Tu	(30min)
Zhi Guo	3-6-2003, Th
Li Zhao	3-6-2003, Th	26, 27
Lan Gao	3-11-2003, Tu	Project Presentation (25 min)
Lingling Jin, Zhi Guo	3-11-2003, Tu	Project Presentation (25 min)
Lan Ye	3-11-2003, Tu	Project Presentation (25 min)
Yan Luo	3-13-2003, Th	Project Presentation (25 min)
Banit Agrawal, Satya Mohanty	3-13-2003, Th	Project Presentation (25 min)
Dinesh C. Suresh	3-13-2003, Th	Project Presentation (25 min)

Project List

Project Descriptions	Project Members
Design a low power data cache for embedded processors	Jia Yu, Shaohui Chen
Test the impact of bus encoding delay on program performance	Lan Gao
Measure the power, delay and area overhead for FV data bus encoder and decoder	Lan Ye
Measure the power, delay and area overhead for FV encoder and decoder using FPGA	Zhi Guo and Lingling Jin
Adopt bus-inversion into FV data bus encoding	Dinesh C. Suresh
Implementing a coarse-grained multithreading RISC processor	Yan Luo, Li Zhao, Ayse Betul Buyukkurt
Implementing "Tag Correlating Prefetcher" in SimpleScalar	Banit Agrawal, Satya Mohanty

Lecture Notes and Reading List

Low Power Cache Designs (1/07/03)
CACTI website:http://research.compaq.com/wrl/people/jouppi/CACTI.html

Readings:
1. "Internal organization of the Alpha 21164 a 300-MHz 64-bit quad-issue CMOS RISC microprocessor,"
  J.H. Edmondson et al., Digital Technical Journal, 7(1), 1995.
2. "SH3: High Code Density, Low Power,"
  A. Hasegawa et al., IEEE Micro, pages 11--19, Dec 1995.
3. "Reducing Set-Associative Cache Energy via Way-Prediction and Selective Direct-Mapping,"
  Michael D. Powell, Amit Agarwal, T. N. Vijaykumar, Babak Falsafi, Kaushik Roy, MICRO'01
4. "Selective Cache Ways: On-Demand Cache Resource Allocation,"
  David H. Albonesi, MICRO'99
5. "Reducing the Frequency of Tag Compares for Low Power I-Cache Design,"
  Ramesh Panwar, David Rennels, ISLPED'95
6. "Direct Addressed Caches for Reduced Power Consumption,"
  Emmett Witchel, Sam Larsen, C. Scott Ananian, Krste Asanovic, MICRO'01
7. "The Filter Cache: An Energy Efficient Memory Structure,"
  Johnson Kin, Munish Gupta, William H. Mangione-Smith, MICRO'97
8. "Reducing Power in Superscalar Processor Caches Using Subbanking, Multiple Line Buffers and Bit-Line Segmentation,"
  Kanad Ghose and Milind B. Kamble, ISLPED'99

Low Power Bus Encoding Techniques (1/09/03)
Readings:
1. "Saving Power in The Control Path of Embedded Processors,"
  C. L. Su, C. Y. Tsui, and A. M. Despain, IEEE Design and Test of Computers, pages 24--30, Vol. 11, 1994.
2. "Asymptotic Zero-Transition Activity Encoding for Address Buses in Low-Power Microprocessor-Based Systems,"
  L. Benini, G. De Micheli, E. Macii, D. Sciuto, C. Silvano, IEEE 7th Great Lakes Symposium on VLSI, Urbana, IL, pp. 77-82, Mar. 1997.
3. "Irredundant Address Bus Encoding for Low Power,"
  Y. Aghaghiri, F. Fallah, and M. Pedram, ACM/IEEE International Symposium on Low Power Electronics and Design, pages 182--187, August 2001.
4. "Bus-invert coding for low-power I/O,"
  M. R. Stan and W. P. Burleson, IEEE Transactions on Very Large Scale Integration (VLSI) Systems, pages 49--58, Vol. 3, 1995.
5. "Synthesis of Low-Overhead Interfaces for Power-Efficient Communication Over Wide Buses,"
  L. Benini, A. Macii, E. Macii, M. Poncino, and R. Scarsi, ACM Design Automation Conference, pages 128--133, 1999.
6. "Power Protocol: Reducing Power Dissipation on Off-Chip Data Buses,"
  K. Basu, A. Choudhary, J. Pisharath, and M. Kandemir, MICRO'35, 2002.

Introduction to MultiThreaded Processors (1/14/03)
Readings:
1. "Simultaneous Multithreading: Maximizing On-Chip Parallelism,"
  D. Tullsen, S. Eggers, and H. Levy, ISCA'95,June 1995, pages 392-403.
2. "Exploiting Choice: Instruction Fetch and Issue on an Implementable Simultaneous Multithreading Processor,"
  D. Tullsen, S. Eggers, J. Emer, H. Levy, J. Lo, and R. Stamm, ISCA'96, pages 191-202.
3. "Converting Thread-Level Parallelism Into Instruction-Level Parallelism via Simultaneous Multithreading,"
  J. Lo, S. Eggers, J. Emer, H. Levy, R. Stamm, and D. Tullsen, ACM Transactions on Computer Systems, August 1997, pages 322-354.
4. "Exploiting Thread-Level Parallelism on Simultaneous Multithreaded Processors,"
  J. Lo's thesis, 1998.
5. "Variability in Architectural Simulations of Multi-threaded Workloads,"
  A. Alameldeen and D. Wood, HPCA9, February 2003.
6. "Mini-threads: Increasing TLP on Small-Scale SMT Processors,"
  J. Redstone, S. Eggers, and H. Levy, HPCA9 February 2003.
7. "Instruction Fetch Deferral using Static Slack,"
  G. A. Muthler, D. Crowe, S. J. Patel, and S. S. Lumetta, MICRO35 November 2002, pages 51--61.
8. "Pointer Cache Assisted Prefetching,"
  J. Collins, S. Sair, B. Calder, and D. M. Tullsen, MICRO35 November 2002, pages 62--73.
9. "Dynamic Speculative Precomputation,"
  J. Collins, D. Tullsen, H. Wang, J. Shen, MICRO34 November, 2001, pages 306--317.
10. "Handling Long-latency Loads in a Simultaneous Multithreading Processor,"
  D. M. Tullsen, J. A. Brown, MICRO34 November, 2001, pages 318--327.

MultiThreaded Processor and Case Study (1/16/03)
Readings:
1. "Critical path analysis of TCP transactions,"
  P. Barford and M. Crovella, IEEE/ACM Transactions on Networking, vol. 9, pp. 238-48, 2001.
2. "The importance of non-data touching processing overheads in TCP/IP,"
  J. Kay and J. Pasquale, Proceedings of ACM SIGCOMM '93
3. "Profiling and reducing processing overheads in TCP/IP,"
  J. Kay and J. Pasquale, IEEE/ACM Transactions on Networking, vol. 4, pp. 817-28, 1996
4. "Speeding up protocols for small messages,"
  T. Blackwell, Proceedings of ACM SIGCOMM'96, ACM, Stanford, CA, USA, 1996.
5. "QoS provisioning in clusters: an investigation of Router and NIC design,"
  Ki Hwan Yum, Eun Jung Kim, Chita R. Das, ISCA'01
6. "Queue pair IP: a hybrid architecture for system area networks,"
  Philip Buonadonna, David Culler, ISCA'02

XScale: Embedded Processor (1/21/03)
Readings:
1. "Low-cost branch folding for embedded applications with small tight loops,"
  L. H. Lee, J. Scott, B. Moyer, J. Arends, MICRO'99.
2. "Understanding multimedia application characteristics for designing programmable media processors,"
  J. Fritts and W. Wolf, Multimedia Hardware Architectures 1999, SPIE, 1999.
3. "Variability in the execution of multimedia applications and implications for architecture,"
  C. J. Hughes, P. K. , S. V. Adve, R. Jain, C. Park, J. Srinivasan, ISCA'01.
4. "TCP: Tag Correlating Prefetchers,"
  Z. Hu, M. Martonosi and S. Kaxiras, HPCA'03.
5. "Using a User-Level Memory Thread for Correlation Prefetching,"
  Y. Solihin, J. Lee, and J. Torrellas, ISCA'02.
6. "Cryptomaniac: A Fast Flexible Architecture for Secure Communications,"
  L. Wu, C. Weaver, and T. Austin, ISCA'01.
7. "Architectural support for fast symmetric-key cryptography,"
  J. Burke, J. McDonald, T. Austin, ASPLOS, 2000.

Additional Readings:

"Fine-grain CAM-tag cache resizing using miss tags,"
Michael Zhang, Krste Asanovic, ISLPED'02
"An adaptive serial-parallel CAM architecture for low-power cache blocks,"
Aristides Efthymiou, Jim D. Garside, ISLPED'02
"A history-based I-cache for low-energy multimedia applications,"
Koji Inoue, V. G. Moshnyaga, K. Murakami, ISLPED'02
"An adaptive, non-uniform cache structure for wire-delay dominated on-chip caches,"
Changkyu Kim, Doug Burger, Stephen W. Keckler, ASPLOS'02
"Concurrency, latency, or system overhead: which has the largest impact on uniprocessor DRAM-system performance?"
V. Cuppu, B. Jacob, ISCA'01.
"Cost-sensitive Cache Replacement Algorithms,"
Jaeheon Jeong and Michel Dubois, HPCA'03
"Generating Physical Addresses Directly for Saving Instruction TLB Energy,"
I. Kadayif, A. Sivasubramaniam, M. T. Kandemir, G. Kandiraju, and G. Che,MICRO35
"Compiler Managed Micro-cache Bypassing for High Performance EPIC Processors,"
Y. Wu, R. Rakvic, L. L. Chen, C. C. Miao, G. Chrysos, J. Fang, MICRO35
"Going the distance for TLB prefetching: an application-driven study,"
G. B. Kandiraju, A. Sivasubramaniam, ISCA'02.
"A stateless, content-directed data prefetching mechanism,"
Robert Cooksey, Stephan Jourdan, Dirk Grunwald, ASPLOS'02

Winter 2003 CS 260 - Advanced Topics in Computer Architecture

Course Load

Presentation Schedule

Project List

Lecture Notes and Reading List

Winter 2003
CS 260 - Advanced Topics in Computer Architecture