CS162
Advanced Design and Architecture of Computer Systems
Spring 2006

General Information

Class Meeting Time:	3:40- 5:00pm, TR
Lecture Room:	PHY 2111
	Engr II 444 after first lecture
Office Hours:	12:00-1:00, TR
Textbook:	John L. Hennessy and David A. Patterson,
	"Computer Organization and Design, The Hardware/Software Interface,"
	3rd Edition. Morgan Kaufmann Publishers, 2004.
	Most material will be provided in lectures.
Prerequisite:	CS161
Moodle System:	http://fish.cs.ucr.edu/moodle/
TA's	San Nguyen
	Responsibilities: help answer questions regarding lectures, homeworks, quizes etc.

Course Requirements:

Syllabus

• Pipeline data path; Data forwarding, stalls, flushing (2.5 weeks);
• Instruction level parallelism (2 week);
• Cache memory: miss reductions; virtual memory (1.5 week);
• I/O system (1 week);
• Introduction to chip multiprocessors (1 week);

Class Schedule:

Announcements:

Homework:

• Homework 1: 6.17, 6.18 on pp. 456 of the textbook. Due: 4/27 before class.
• Homework 2: multicycle staged pipeline. Due: 5/9 before class.
• Homework 3: Tomasulo's algorithm. Assigned: 5/17/2006. Due: 5/25/2006, in class.
• Homework 4: Virtual memory. Assigned: 5/26. Due 6/1 in class.
• Homework 5: read the example on pp. 601 of the textbook. Recalculate the result using a memory backplane bus transfer rate of 500MB/sec, i.e., the originial rate has been cut by half.
  Assigned 6/1, due 6/8 in class.

Policies:

• You are responsible for all material covered in lectures.
• You may discuss assignments with classmates, but the work you turn in must be your own. Cheating in homework, quizes, labs, and exams are absolutely prohibited. The minimum penalty for a violation of the regulations will be a zero for the assignment; the maximum penalty will be failure of the course.
• Examinations must be taken in class on the day they are given. There will be no exceptions.