CS203 Fall 2003 Project Description
Due: 12pm, December 8th, 2003

You will form a group of 3 people. Each person must read 1 paper or more (for better understanding). You will write up a report on the papers you read. The structure of the report must follow these rules:

• Each person should write a section summarizing the essence of the paper. The section title should be tagged with the person's name. Avoid taking text directly from the paper since this is considered plagiarism (I will read those papers too). The quality of this section determines your base score of the project. Thus, different members in a group may get different scores. (50%)
• The three of you must also come up with a section comparing the three papers, elaborating the differences, advantages and disadvantages. The quality of this part will determine your analysis part of the project score. All members get the same score since it's a joint effort from the group. (25%)
• If an individual is able to read more relavant papers on the topic and write down additional sections (tagged with author's name) expanding your understanding of this topic, it will be considered as the thorough part of the project score. (25%)
• Alternatively, you can also try some programming (Yeah!) to test some of your thoughts/ideas or prove/disprove the paper authors results, it will be considered as the creative part of the project score. (25%)
• Format: 5 pages, double column, 10 or 11pt font size, single or 1.5 line spacing, 6x8in text body, around 2500 words.

TOPICS

• Pipeline depth, clock frequency, and processor performance (Haifeng Li,...)
  • "The optimum pipeline depth for a microprocessor", A. Hartstein, Thomas R. Puzak, ISCA 2002.
  • "The optimal logic depth per pipeline stage is 6 to 8 FO4 inverter delays", M. S. Hrishikesh, Doug Burger, Norman P. Jouppi, Stephen W. Keckler, Keith I. Farkas, Premkishore Shivakumar, ISCA 2002.
  • "Increasing processor performance by implementing deeper pipelines" Eric Sprangle, Doug Carmean, ISCA 2002.
• Play with instructions (Thomas Repantis, Yannis Drougas, Kyriakos Kareno)
  • "An empirical analysis of instruction repetition", Avinash Sodani, Gurindar S. Sohi, ASPLOS 1998.
  • "Dynamic Instruction Reuse", Avinash Sodani and Gurindar S. Sohi, ISCA, June 1997
  • "Exceeding the Dataflow Limit via Value Prediction", M. H. Lipasti, J. P. Shen, 1996.
  • "Understanding the differences between value prediction and instruction reuse" Avinash Sodani, Gurindar S. Sohi, MICRO 1998.
• Superscalar processor (Luke Keppler Haitao Qiu, and Ya-Lee Tsai)
  • "The Microarchitecture of Superscalar Processors" J. E. Smith and G. S. Sohi, in Proceedings of the IEEE, December 1995.
  • "Implementing register interlocks in parallel-pipeline, multiple instruction queue, superscalar processors", S. Weiss, HPCA 1995.
  • "An empirical study of decentralized ILP execution models", Narayan Ranganathan, Manoj Franklin, ASPLOS 1998.
• Register renaming (Sitanshu Kumar, Anwar Adi, ilker Basaran)
  • "Register Renaming and Dynamic Speculation: an Alternative Approach", Mayan Moudgill, Keshav Pingali, Stamatis Vassiliadis, MICRO 1993.
  • "A Novel Renaming Scheme to Exploit Value Temporal Locality through Physical Register Reuse and Unification", S. Jourdan, R. Ronen, M. Bekerman, B. Shomar, A. Yoaz, MICRO 1998.
  • "Scalable Register Renaming via the Quack Register File", B. Black, J. P. Shen, Technical Report: CMuART-2000-01.
  • "Improving the accuracy and performance of memory communication through renaming" Gary S. Tyson, Todd M. Austin, MICRO 1997.
• Branch prediction (Wesley Huie, Dale Kim, Huchi Hsu)
  • "Multiple-block ahead branch predictors", A. Seznec, S. Jourdan, P. Sainrat, and P. Michaud, ASPLOS 1996.
  • "A mechanism for reducing negative branch history interference", E. Sprangle, R. chappell, M. Alsup, and Y. N. Patt, ISCA 1997.
  • "The Impact of Delay on the Design of Branch Predictors", Daniel A. Jiménez, Stephen W. Keckler, and Calvin Lin, MICRO 2000.
  • "Improving prediction for procedure returns with return-address-stack repair mechanisms", Kevin Skadron, Pritpal S. Ahuja, Margaret Martonosi, Douglas W. Clark, MICRO 1998.
• Prefetching (Abhishek Mitra, SOM NEEMA, Keri Nishimoto)
  • "Wrong-path instruction prefetching", Jim Pierce, Trevor Mudge, MICRO 1996.
  • "Tango: a hardware-based data prefetching technique for superscalar processors", Shlomit S. Pinter, Adi Yoaz, MICRO 1996.
  • "Distributed prefetch-buffer/cache design for high performance memory systems", T. Alexander, G. Kedem, HPCA 1996.
• Write Buffer
  • "Design issues and tradeoffs for write buffers", K. Skadron, D. W. Clark, HPCA 1997.
  • "Improving I/O performance with a conditional store buffer", Lambert Schaelicke, Al Davis, MICRO 1998.
• Trace caches, and instruction caches (David, Dan, Titus)
  • "Trace cache: a low latency approach to high bandwidth instruction fetching" Eric Rotenberg, Steve Bennett, James E. Smith, MICRO 1996.
  • "Path-based next trace prediction", Quinn Jacobson, Eric Rotenberg, James E. Smith, MICRO 1997.
  • "Putting the fill unit to work: dynamic optimizations for trace cache microprocessors" Daniel Holmes Friendly, Sanjay Jeram Patel, Yale N. Patt, MICRO 1998.
  • "Temporal-based procedure reordering for improved instruction cache performance" J. Kalamationos, D. R. Kaeli, HPCA 1998.
• Code Compression for better instruction cache performance (Nitin Kumar, Anup Mayank, Honomount Rawat)
  • "Improving code density using compression techniques", Charles Lefurgy, Peter Bird, I-Cheng Chen, Trevor Mudge, MICRO 1997.
  • "Procedure based program compression" Darko Kirovski, Johnson Kin, William H. Mangione-Smith, MICRO 1997.
  • "Code compression based on operand factorization" Guido Araujo, Paulo Centoducatte, Mario Cartes, Ricardo Pannain, MICRO 1998.
• Cache performance (Nan, Yihua, Song)
  • "Hardware identification of cache conflict misses", Jamison D. Collins, Dean M. Tullsen, MICRO 1999.
  • "Eager writeback - a technique for improving bandwidth utilization" Hsien-Hsin S. Lee, Gary S. Tyson, Matthew K. Farrens, MICRO 2000.
  • "Avoiding initialization misses to the heap", Jarrod A. Lewis, Bryan Black, Mikko H. Lipasti, ISCA 2002.
• Cache TLB (2) (Kin Fai Kan, Mirella, Jeff)
  • "Data cache locking for higher program predictability", Xavier Vera, BjöLisper, Jingling Xue , SIGMETRICS 2003.
  • "Characterizing the d-TLB behavior of SPEC CPU2000 benchmarks", Gokul B. Kandiraju, Anand Sivasubramaniam, SIGMETRICS 2002.
  • "Generating physical addresses directly for saving instruction TLB energy", I. Kadayif, A. Sivasubramaniam, M. Kandemir, G. Kandiraju, G. Chen, MICRO 2002.
• Graphics processors (Chris, Tim, Matt)
  • "A superscalar 3D graphics engine" Andrew Wolfe, Derek B. Noonburg, MICRO 1999.
  • "Dynamic 3D graphics workload characterization and the architectural implications", Tulika Mitra, Tzi-cker Chiueh, MICRO 1999.
  • "Using modern graphics architectures for general-purpose computing: a framework and analysis" Chris J. Thompson, Sahngyun Hahn, Mark Oskin, MICRO 2002.
• Multimedia and Graphics (Ulises, Anna, Paul)
  • "Saving energy with architectural and frequency adaptations for multimedia applications", C. J. Hughes, J. Srinivasan, S. V. Adve, MICRO 2001.
  • "Enhancing loop buffering of media and telecommunications applications using low-overhead predication", John W. Sias, Hillery C. Hunter, Wen-mei W. Hwu, MICRO 2001.
  • "ZR: a 3D API transparent technology for chunk rendering", Emile Hsieh, Vladimir Pentkovski, Thomas Piazza, MICRO 2001.
• Energy efficient designs (Li, Jinnan, Xiaopeng)
  • "Analyzing Energy Behavior of Spatial Access Methods for Memory-Resident Data", VLDB 2001 N. An, A. Sivasubramaniam, N. Vijaykrishnan, M. Kandemir, M. J. Irwin, S. Gurumurthi,
  • "Memory hierarchy reconfiguration for energy and performance in general-purpose processor architectures", R. Balasubramonian, D. Albonesi, A. Buyuktosunoglu, S. Dwarkadas, MICRO 2000.
  • "Power protocol: reducing power dissipation on off-chip data buses", K. Basu, A. Choudhary, J. Pisharath, M. Kandemir, MICRO 2002.