CS161
Design and Architecture of Computer Systems
Winter 2004

General Information

Instructor: Jun Yang
Office: SURGE 318
Telephone: 951-827-2558
Email: junyang@cs.ucr.edu

Class Meeting Time: 11:10-12:30pm, TR
Lecture Room: SPR 2355
Office Hours: 1:30-2:30, TR
Textbook: John L. Hennessy and David A. Patterson,
"Computer Organization and Design, The Hardware/Software Interface,"
3rd Edition. Morgan Kaufmann Publishers, 2004.
Reference Books (not required): Hans-Peter Messmer
"The Indispensable PC Hardware Book,"
4th Edition. Addison-Wesley, 2001.
Prerequisite: CS120B OR EE120B
Blackboard System: http://www.ilearn.ucr.edu/
TA's Wei Wu: discussion session 4:10-5, BRNHL B255.
Responsibilities: help answer questions regarding lectures, homeworks, quizes etc.

Course Requirements:

Homework (4) 20%
Quizes (2) 40% Quize 1: 1/27, Th; Answer Quize 2: 2/24, Th (tentative date)
Final: 3/17, 11:30 to 1:30 40%

Class Notes:

Lecture 1: Introduction and ISA
Lecture 2: ISA-2
Lecture 3: ISA-3
Lecture 4: ISA-4, Performance
Lecture 5: Floating Point numbers(updated)
Lecture 6: One-cycle Data Path
Lecture 7: Multi-cycle Data Path
Lecture 8: Multi-cycle Control Generation
Lecture 10: Microprogramming
Lecture 11: Introduction to Caches
Lecture 12: More on Caches
Lecture 13: Write Policies
Lecture 14: Memory Performance
Lecture 15: Pipelining 1
Lecture 16: Pipelining 2

Announcements:

Homework:

Homework 1 Assigned: 1/11/2005. Due: 1/18/2005, in class.
Homework 2: Performace evaluation and Amdahl's law. Exercise 4.12 on page 274 (3rd. of the book). Assigned: 1/18/2005. Due: 1/25/2005, in class.
Homework 3: Multicycle data path and control path: 5.36 on page 357. Assigned: 2/10/2005. Due: 2/17/2005, in class. Answer
Homework 4: See slide #22 in Lecture 15. Assigned: 3/8/2005. Due 3/14/2005 11am by email.

Exercises (practise on your own):

Policies: