CS161
Design and Architecture of Computer Systems
Spring 2004

General Information

Instructor: Jun Yang
Office: SURGE 318
Telephone: 909-787-2558
Email: junyang@cs.ucr.edu

Class Meeting Time: 2:10-3:30pm, TR
Lecture Room: OLMH 1212
Office Hours: 3:30-5:00, TR
Textbook: John L. Hennessy and David A. Patterson,
"Computer Organization and Design, The Hardware/Software Interface,"
2nd Edition. Morgan Kaufmann Publishers, 1998.
Reference Books: Hans-Peter Messmer
"The Indispensable PC Hardware Book,"
4th Edition. Addison-Wesley, 2001.
Prerequisite: (CS061 (C- or better) AND CS120A) OR EE120A
Blackboard System: http://www.ilearn.ucr.edu/
TA's Jia Yu: Office hours Friday 11-1 Surge 281
Satya Mohanty: Office hours Wednesday 2-3pm Surge 281
Lab meeting time: W, 11:10-2pm Surge 171 (TA: Jia Yu); Fri, 8:10-11pm Surge 170 (TA: Satya Mohanty); Fri, 8:10-11am Surge 171 (TA: Jia Yu)
Lab attendance is mandatory. You are expected to stay in the lab for the entire lab session, working on material related to this course. Part of your lab grade is based on attendance and participation

Course Requirements:

Homework 10%
Labs and Quizes 40%
Midterm 1 25% (Date: 5/4/2004)
Midterm 2 25% (Tentative Date: 6/3/2004)

Class Notes:

Chapter 1-4 Six slides per page, One slide per page
Chapter 5 (part 1) Six slides per page, One slide per page
Chapter 5 (part 2) Six slides per page, One slide per page
Chapter 5 (part 3 ) Six slides per page, One slide per page
Chapter 5 (part 4 ) Six slides per page, One slide per page
Chapter 6 (part 1 ) Six slides per page, One slide per page
Chapter 7 (part 1 ) Six slides per page, One slide per page

Announcements:

Quiz 1 will be on 4/15/04, in class. The material covered will be until the lecture on 4/13/04.
The summary slides from each lecture review (updated)
The note slides are here (updated)

Quiz 2 will be on 5/20/04, in class. The material covered will be until the lecture on 5/18/04.
The summary slides from each lecture review

Homework:

Homework1 (Assigned 4/1/2004, Due: 4/8/2004 2:10pm):
Suppose that a program runs 2 seconds on machine A. It executs 1G cycles in total. What is the clock frequency of A? We are now experimenting a new version of machine A. The targeting clock frequency is 1.5 times higher than A. But the program would run for 1.5G cycles now. Is the new version faster or slower? And by how much? Solution

Homework2 (Assigned on 4/22/2004, Due: 4/29/2004):
On page 82 of the lecture notes, the implementation of "slt" in figure (b) did not consider the situation when an overflow occurs. The problem asks you to change figure (b) so that the "set" output takes into account the "overflow" output.

Homework 3 (Assigned on 5/6/2004, Due: 5/13/2004):
Exercise 5.5 on page 427 in the textbook.
Solution: No additions to the datapath are required. A new row should be added to the truth table in Figure 5.20. The new control is similar to load word because we want to use the ALU to add the immediate to a register( and thus RegDst = 0, ALUSrc = 1, ALUOp = 00). The new control is also similar to an R-format instruction, because we want to write the result of the ALU into a register (and thus MemtoReg = 0, RegWrite = 1) and of course we aren't branching or using memory (Branch = 0, MemRead = 0, MemWrite = 0).

Exercises (practise on your own):

Problem 2.15 and 2.16 on page 92 and 93 in the textbook. Solution
Problem 3.9 on page 199 in the textbook. Solution
Problem 4.14 on page 324 in the textbook.

Policies: