Names: John Doe, Jane Smith
Login: jdoe, jsmith
Email: jdoe@cs.ucr.edu, jsmith@cs.ucr.edu
Lab Section: 0##
Assignment: Lab #
I acknowledge all content is original.

I. Lab objective
The lab objective was to introduce us to using Xilinx ISE 13 tool-chain.

II . Personal contributions
The work was shared for this exercise. As a group we followed the steps to create a Xilinx project, synthesize, test, and place & route the design. John Doe actually created the files on the computer, while Jane Smith aided in following steps to complete the lab.

III. Skill learned & knowledge gained.
Not having worked with the Xilinx tool-chain before, I learned how to create a project, add new vhdl source files, create a testbench, simulate VHDL source code, synthesize,and place and route. The tool-chain most difficult part was running the simulation because the first time the program did not operate correctly. After some trouble-shooting we found the simulation process was active but not accessing the correct file. To fix the error we killed all processes to Xilinx and the reloaded the project. Overlooking the code, I learned how to make a concurrent and sequential statements within VHDL, as well as a simple testbench. The features of Xilinx GUI made programming in VHDL easy and I still want to explore the other tools within the tool-chain. After reading the Xilinx documentation, I understand many of the other features such as core generator and language templates.

IV. Known bugs locations
We tested our design with all possible cases, therefore are no known bugs.

V. Feedback on the lab
Overall the lab was great!