LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_ARITH.ALL;
 
ENTITY synbc_ramtb IS
END synbc_ramtb;
 
ARCHITECTURE behavior OF synbc_ramtb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT sync_ram
    generic (	
		ADDRESS_WIDTH : integer	:= 4;
		DATA_WIDTH    : integer	:= 8
    );
    port (
		Clock : in  std_logic;
		Reset : in  std_logic;
		Enable : in  std_logic;
		Write_Enable : in  std_logic;
		Address : in  std_logic_vector(ADDRESS_WIDTH-1 downto 0);
		Datain : in  std_logic_vector(DATA_WIDTH-1 downto 0);
		Dataout : out std_logic_vector(DATA_WIDTH-1 downto 0)
    );
    END COMPONENT;

   constant ADDRESS_WIDTH : integer := 5;
	constant DATA_WIDTH : integer := 8;
	constant ADDRESS_RANGE : integer := (2**(ADDRESS_WIDTH)-1);

   --Inputs
   signal Clock : std_logic := '0';
   signal Reset : std_logic := '0';
   signal Enable : std_logic := '0';
   signal Write_Enable : std_logic := '0';
   signal Address : std_logic_vector(ADDRESS_WIDTH-1 downto 0) := (others => '0');
   signal Datain : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');

 	--Outputs
   signal Dataout : std_logic_vector(DATA_WIDTH-1 downto 0);

   -- Clock period definitions
   constant Clock_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: sync_ram
	GENERIC MAP(
	ADDRESS_WIDTH => ADDRESS_WIDTH,
	DATA_WIDTH => DATA_WIDTH
	)
	PORT MAP (
          Clock => Clock,
          Reset => Reset,
          Enable => Enable,
          Write_Enable => Write_Enable,
          Address => Address,
          Datain => Datain,
          Dataout => Dataout
        );

   -- Clock process definitions
   Clock_process :process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin	
      Reset <= '1';
      Enable <= '0';
      Write_Enable <= '0';
      Address <= (others => '0');
      Datain <= (others => '0');
      wait for 10 ns;
		Reset <= '1';
      Enable <= '1';
      Write_Enable <= '0';
      Address <= (others => '0');
      Datain <= (others => '0');
		wait for 10 ns;

		--Verifying the reset state
      Reset <= '1';
      Enable <= '1';
      Write_Enable <= '0';
      Address <= (others => '0');
      Datain <= (others => '0');
		wait for Clock_period;
      assert(Dataout = "ZZZZZZZZ")
		   report("Error at Reset State")
			severity ERROR;
			
		--Check if all ram cells reset
		for I in 0 to ADDRESS_RANGE loop
         Reset <= '0';
         Enable <= '1';
         Write_Enable <= '0';
         Address <= conv_std_logic_vector(I,ADDRESS_WIDTH);
         Datain <= (others => 'Z');
		   wait for Clock_period;
         assert(Dataout = conv_std_logic_vector(0,DATA_WIDTH))
		      report("Error after reset data check with ADDRESS=" & integer'image(I) & ".")
			   severity ERROR;
		end loop;
		
		--Testing read on the ram cells
		--Filling ram cells with data
		for I in 0 to ADDRESS_RANGE loop
         Reset <= '0';
         Enable <= '1';
         Write_Enable <= '1';
         Address <= conv_std_logic_vector(I,ADDRESS_WIDTH);
         Datain <= conv_std_logic_vector(I*2,DATA_WIDTH);
		   wait for Clock_period;
		end loop;
		--Checking ram Cells with data
		for I in 0 to ADDRESS_RANGE loop
         Reset <= '0';
         Enable <= '1';
         Write_Enable <= '0';
         Address <= conv_std_logic_vector(I,ADDRESS_WIDTH);
         Datain <= (others => 'Z');
		   wait for Clock_period;
         assert(Dataout = conv_std_logic_vector(I*2,DATA_WIDTH))
		      report("Error in reading correct data at ADDRESS=" & integer'image(I) & ".")
			   severity ERROR;
		end loop;
		
      report("End of Testbench") severity NOTE;
      wait;
   end process;

END;