LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.STD_LOGIC_ARITH.ALL;
 
ENTITY sync_fifo_tb IS
END sync_fifo_tb;
 
ARCHITECTURE behavior OF sync_fifo_tb IS 
 
 	--Constants for Ranging
   constant ADDRESS_WIDTH : integer := 3;
	constant DATA_WIDTH : integer := 4;
	constant ADDRESS_RANGE : integer := (2**(ADDRESS_WIDTH)-1);
 
    -- Component Declaration for the Unit Under Test (UUT) 
	component sync_fifo is
	generic (	
		ADDRESS_WIDTH : integer	:= 8; -- Depth of the FIFO := 2^(ADDRESS_WIDTH) - 1
		DATA_WIDTH    : integer	:= 16 -- Width of the data
	);
	port (
		Clock : in  std_logic;
		Reset : in  std_logic;
		Write_Enable : in  std_logic;
		Write_Data : in  std_logic_vector(DATA_WIDTH-1 downto 0);
		Read_Enable : in  std_logic;
		Read_Data : out std_logic_vector(DATA_WIDTH-1 downto 0);
		Full : out std_logic;
		Empty : out std_logic
	);
	end component sync_fifo;

   --Inputs
   signal Clock : std_logic := '0';
   signal Reset : std_logic := '0';
   signal Write_Enable : std_logic := '0';
   signal Write_Data : std_logic_vector(DATA_WIDTH-1 downto 0) := (others => '0');
   signal Read_Enable : std_logic := '0';

 	--Outputs
   signal Read_Data : std_logic_vector(DATA_WIDTH-1 downto 0);
   signal Full : std_logic;
   signal Empty : std_logic;

   -- Clock period definitions
   constant Clock_period : time := 10 ps;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
	uut : 
	sync_fifo
	generic map(	
		ADDRESS_WIDTH => ADDRESS_WIDTH,
		DATA_WIDTH => DATA_WIDTH
	)
	port map (
          Clock => Clock,
          Reset => Reset,
          Write_Enable => Write_Enable,
          Write_Data => Write_Data,
          Read_Enable => Read_Enable,
          Read_Data => Read_Data,
          Full => Full,
          Empty => Empty
	);

   -- Clock process definitions
   Clock_process :process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100 ns.
		Reset <= '1';
		Write_Enable <= '0';
		Write_Data <= (others => '0');
		Read_Enable <= '0';
      wait for Clock_period;

		--Verifying the reset state
		Reset <= '1';
		Write_Enable <= '0';
		Write_Data <= (others => '0');
		Read_Enable <= '0';
		wait for Clock_period;
      assert(Read_Data = conv_std_logic_vector(0,DATA_WIDTH))
		   report("Error at Reset State")
			severity ERROR;
		wait for Clock_period;

		--Push data onto FIFO
		for I in 0 to ADDRESS_RANGE loop
         Reset <= '0';
         Write_Enable <= '1';
			Write_Data <= conv_std_logic_vector(I,DATA_WIDTH);
			Read_Enable <= '0';
		   wait for Clock_period;
         assert(Read_Data = conv_std_logic_vector(0,DATA_WIDTH))
		      report("Error on push I=" & integer'image(I) & ".")
			   severity ERROR;
		end loop;

		
		--POP data from FIFO
		for I in 0 to ADDRESS_RANGE loop
         Reset <= '0';
         Write_Enable <= '0';
			Write_Data <= (others => '0');
			Read_Enable <= '1';
		   wait for Clock_period;
         assert(Read_Data = conv_std_logic_vector(I,DATA_WIDTH))
		      report("Error on pop I=" & integer'image(I) & ".")
			   severity ERROR;
		end loop;

      Reset <= '0';
      Write_Enable <= '0';
		Write_Data <= (others => '0');
		Read_Enable <= '0';
      wait;
   end process;

END;