library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.NUMERIC_STD.ALL;

entity sync_fifo is
	generic (	
		ADDRESS_WIDTH : integer	:= 8; -- Depth of the FIFO := 2^(ADDRESS_WIDTH) - 1
		DATA_WIDTH    : integer	:= 16 -- Width of the data
	);
	port (
		Clock : in  std_logic;
		Reset : in  std_logic;
		Write_Enable : in  std_logic;
		Write_Data : in  std_logic_vector(DATA_WIDTH-1 downto 0);
		Read_Enable : in  std_logic;
		Read_Data : out std_logic_vector(DATA_WIDTH-1 downto 0);
		Full : out std_logic;
		Empty : out std_logic
	);
end sync_fifo;

architecture RTL of sync_fifo is

	--Ram data array
   type ram_type is array ( 0 to (2**ADDRESS_WIDTH)-1 ) of std_logic_vector( (DATA_WIDTH-1) downto 0 );
   signal ram : ram_type := ( others => (others => '0'));

	--Intermediate signal for data output
   signal read_data_s : std_logic_vector( (DATA_WIDTH-1) downto 0 ) := (others => '0');
	
	--Constant values used in comparison
	constant ZEROS : std_logic_vector( ADDRESS_WIDTH downto 0 ) := (others => '0');
		
	--Internal Signals
	signal counter : std_logic_vector( ADDRESS_WIDTH downto 0 ) := (others => '0');
	signal write_ptr : std_logic_vector( (ADDRESS_WIDTH-1) downto 0) := (others => '0');
	signal read_ptr : std_logic_vector( (ADDRESS_WIDTH-1) downto 0) := (others => '0');
	signal full_s : std_logic := '0';
	signal empty_s : std_logic := '0';
	
	--Tracing signals
	--signal write_enable_s : std_logic;
	--signal active_addr_s : std_logic_vector( ADDRESS_WIDTH-1 downto 0 );
begin
   PushFIFO : 
	Process(Clock, Reset)
   begin
		Clocking : 
      if(Clock'event and Clock = '1')then
         Resetting : 
			if(Reset = '1')then
				for I in 0 to ((2**ADDRESS_WIDTH)-1)loop
               ram(I) <= (others => '0');
            end loop;
				write_ptr <= (others => '0');
				counter <= (others => '0');
         else
				Writing :
				If Write_Enable = '1' and full_s = '0' then
					ram(to_integer(unsigned(write_ptr))) <= Write_data;
					write_ptr <= std_logic_vector(unsigned(write_ptr) + 1);
					counter <= std_logic_vector(unsigned(counter) + 1);
            end if Writing;
         end if Resetting;
      end if Clocking;
   end process PushFIFO;

   PopFIFO : 
	Process(Clock, Reset)
   begin
		Clocking : 
      if(Clock'event and Clock = '1')then
         Resetting : 
			if(Reset = '1')then
				read_data_s <= (others => '0');
				read_ptr <= (others => '0');
         else
				Reading :
				If Read_Enable = '1' and empty_s = '0' then
					read_data_s <=  ram(to_integer(unsigned(read_ptr)));
					read_ptr <= std_logic_vector(unsigned(read_ptr) + 1);
            end if Reading;
         end if Resetting;
      end if Clocking;
   end process PopFIFO;

--Combinational
-----------------------------------------------------------
	empty_s <= '1' when ( counter = ZEROS ) else '0';
	full_s  <= Counter(ADDRESS_WIDTH);
	
	--Tracing signals
	--write_enable_s <= '1' when ( Write_Enable = '1' and Full_s = '0') else '0';
	--active_addr_s  <= write_ptr  when ( Write_Enable = '1') else read_ptr;
--Output port mapping
	Full <= full_s;
	Empty <= empty_s;
	Read_Data <= read_data_s;
	
end RTL;