LIBRARY ieee; USE ieee.std_logic_1164.ALL; ENTITY pass_thru_tb IS END pass_thru_tb; ARCHITECTURE behavior OF pass_thru_tb IS -- Component Declaration for the Unit Under Test (UUT) COMPONENT pass_thru PORT( button_north : IN std_logic; button_south : IN std_logic; button_west : IN std_logic; button_east : IN std_logic; switches : IN std_logic_vector(3 downto 0); leds : OUT std_logic_vector(7 downto 0) ); END COMPONENT; --Inputs signal button_north : std_logic := '0'; signal button_south : std_logic := '0'; signal button_west : std_logic := '0'; signal button_east : std_logic := '0'; signal switches : std_logic_vector(3 downto 0) := (others => '0'); --Outputs signal leds : std_logic_vector(7 downto 0); --Clock signal clock : std_logic := '0'; constant clock_period : time := 20 ns; BEGIN -- Instantiate the Unit Under Test (UUT) uut: pass_thru PORT MAP ( button_north => button_north, button_south => button_south, button_west => button_west, button_east => button_east, switches => switches, leds => leds ); -- Clock process definitions clock_process :process begin clock <= '0'; wait for clock_period/2; clock <= '1'; wait for clock_period/2; end process; -- Stimulus process stim_proc: process begin -- hold reset state for 10 ns. button_north <= '0'; button_south <= '0'; button_west <= '0'; button_east <= '0'; switches <= X"0"; wait for 10 ns; wait for clock_period; -- insert stimulus here --Error Check OFF button_north <= '0'; button_south <= '0'; button_west <= '0'; button_east <= '0'; switches <= X"0"; wait for clock_period; Assert ( leds = X"00" ) Report "Error : leds = x00" Severity ERROR; --Error Check ON button_north <= '1'; button_south <= '1'; button_west <= '1'; button_east <= '1'; switches <= X"F"; wait for clock_period; Assert ( leds = X"FF" ) Report "Error : leds = xFF" Severity ERROR; wait; end process; END;