LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;

ENTITY matchfsm_tb_vhd IS
END match_tb_vhd;

ARCHITECTURE behavior OF matchfsm_tb_vhd IS 

	COMPONENT matchfsm
	PORT(
		clock : IN std_logic;
		reset : IN std_logic;
		input : IN std_logic;          
		match : OUT std_logic
		);
	END COMPONENT;

	--Inputs
	SIGNAL clock :  std_logic := '0';
	SIGNAL reset :  std_logic := '0';
	SIGNAL input :  std_logic := '0';

	--Outputs
	SIGNAL match :  std_logic;

BEGIN

	-- Instantiate the Unit Under Test (UUT)
	uut: matchfsm PORT MAP(
		clock => clock,
		reset => reset,
		input => input,
		match => match
	);
	
	process
	begin
		clock <= '0';
		wait for 5 ns;
		clock <= '1';
		wait for 5 ns;
	end process;

	tb : PROCESS
	BEGIN
		-- reset
		reset <= '1';
		wait for 20 ns;
		reset <= '0';
		-- input pattern and check output along the way
		-- 001101010111001110111
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		-- HERE IS THE MATCH
		input <= '1';
		wait for 10 ns;
		assert (match = '1') report "false negative" severity error;
		--
		input <= '0';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		input <= '1';
		wait for 10 ns;
		assert (match = '0') report "false positive" severity error;
		--
		report "end of testbench" severity note;
		wait; -- will wait forever
	END PROCESS;

END;