LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
 
ENTITY scounter32_tb IS
END scounter32_tb;
 
ARCHITECTURE behavior OF scounter32_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT scounter32
    PORT(
         Clock : IN  std_logic;
         Reset : IN  std_logic;
         Enable : IN  std_logic;
         Count : OUT  std_logic_vector(31 downto 0);
         Overflow : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal Clock : std_logic := '0';
   signal Reset : std_logic := '0';
   signal Enable : std_logic := '0';

 	--Outputs
   signal Count : std_logic_vector(31 downto 0);
   signal Overflow : std_logic;

   -- Clock period definitions
   constant Clock_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: scounter32 PORT MAP (
          Clock => Clock,
          Reset => Reset,
          Enable => Enable,
          Count => Count,
          Overflow => Overflow
        );

   -- Clock process definitions
   Clock_process :process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 10 ns.
		Reset <= '1';
		Enable <= '0';
      wait for 10 ns;

      -- insert stimulus here
		
		--Error Check for ranged additions
		for N in 1 to 1024 loop
			Reset <= '0';											--Set input to N with 32 bit range
			Enable <= '1';											--Set input to M with 32 bit range
			wait for clock_period;								--Wait for gate delay
			--If not correct then report Error
			Assert ( Count = conv_std_logic_vector(N,32) and 
						Overflow = '0' ) 							--Count check with N value
				Report "Error at" & " Count=" &
						 integer'image(N) & "."					--Report Count error value to command line.
				Severity ERROR;									--Type of severity to report
		end loop;

		--Check Enable Hold
		Reset <= '0';											--Set input to N with 32 bit range
		Enable <= '0';											--Set input to M with 32 bit range
		wait for clock_period;								--Wait for gate delay
		--If not correct then report Error
		Assert ( Count = conv_std_logic_vector(1024,32) and 
					Overflow = '0' )
			Report "Error at Enable Hold."
			Severity ERROR;									--Type of severity to report
	--Systems runs for (10ns)*(1+N+1) = ? ns

	Report "Completed Testbench." Severity NOTE; 		--Report testbench complete.
   wait;
   end process;

END;