LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;
 
ENTITY sreg32_tb IS
END sreg32_tb;
 
ARCHITECTURE behavior OF sreg32_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
    COMPONENT sreg32
    PORT(
         Clock : IN  std_logic;
         Reset : IN  std_logic;
         Load : IN  std_logic;
         Input : IN  std_logic_vector(31 downto 0);
         Output : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    
   --Inputs
   signal Clock : std_logic := '0';
   signal Reset : std_logic := '0';
   signal Load : std_logic := '0';
   signal Input : std_logic_vector(31 downto 0) := (others => '0');
 	--Outputs
   signal Output : std_logic_vector(31 downto 0);
   -- Clock period definitions
   constant Clock_period : time := 10 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: sreg32 PORT MAP (
          Clock => Clock,
          Reset => Reset,
          Load => Load,
          Input => Input,
          Output => Output
        );

   -- Clock process definitions
   Clock_process : process
   begin
		Clock <= '0';
		wait for Clock_period/2;
		Clock <= '1';
		wait for Clock_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
     -- hold reset state for 10 ns.
	  	Reset <= '1';
		Load <= '0';
		Input <= conv_std_logic_vector(0,32);
      wait for 10 ns;
		
      -- insert stimulus here

		--Error Load 1
		Reset <= '0';
		Load <= '1';
		Input <= X"FFFFFFFF";					--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( Output = X"FFFFFFFF" ) 		--Output check
			Report "Error at Load 1."				--Report to command line
			Severity ERROR;						--Type of severity to report

		--Error Keep 1
		Reset <= '0';
		Load <= '0';
		Input <= X"FFFF0000";					--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( Output = X"FFFFFFFF" ) 		--Output check
			Report "Error at Keep 1."				--Report to command line
			Severity ERROR;						--Type of severity to report

		--Error Reset
		Reset <= '1';
		Load <= '1';
		Input <= X"0000FFFF";					--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( Output = X"00000000" ) 		--Output check
			Report "Error at Reset 1."				--Report to command line
			Severity ERROR;						--Type of severity to report

		--Error Load 2
		Reset <= '0';
		Load <= '1';
		Input <= X"89ABCDEF";					--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( Output = X"89ABCDEF" ) 		--Output check
			Report "Error at Load 2."				--Report to command line
			Severity ERROR;						--Type of severity to report

		--Error Keep 2
		Reset <= '0';
		Load <= '0';
		Input <= X"12439226";					--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( Output = X"89ABCDEF" ) 		--Output check
			Report "Error at Keep 2."				--Report to command line
			Severity ERROR;						--Type of severity to report
			
		--Error Reset 2
		Reset <= '1';
		Load <= '0';
		Input <= X"ABCDEF00";					--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( Output = X"00000000" ) 		--Output check
			Report "Error at Reset 2."				--Report to command line
			Severity ERROR;						--Type of severity to report

	Report "Completed Testbench." Severity NOTE; 		--Report testbench complete.
   wait;
   end process;

END;