LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_arith.ALL;

ENTITY adder32_tb IS
END adder32_tb;
 
ARCHITECTURE behavior OF adder32_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT adder32
    PORT(
         A : IN  std_logic_vector(31 downto 0);
         B : IN  std_logic_vector(31 downto 0);
         S : OUT  std_logic_vector(31 downto 0);
         Overflow : OUT  std_logic
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic_vector(31 downto 0) := (others => '0');
   signal B : std_logic_vector(31 downto 0) := (others => '0');
 	--Outputs
   signal S : std_logic_vector(31 downto 0);
   signal Overflow : std_logic;
	--Clock
	signal clock : std_logic := '0';
	constant clock_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: adder32 PORT MAP (
          A => A,
          B => B,
          S => S,
          Overflow => Overflow
        );

	-- Clock Process
	clock_process : process
		begin
			clock <= '0';
			wait for clock_period/2;
			clock <= '1';
			wait for clock_period/2;
	end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 10 ns.
		A <= X"00000000";
		B <= X"00000000";
      wait for 10 ns;
		
      -- insert stimulus here
		
		--Error Check Max
		A <= X"FFFFFFFE";										--Set input
		B <= conv_std_logic_vector(1,32);				--Set input
		wait for clock_period;								--Wait for gate delay
		--If not correct then report Error
		Assert ( S = X"FFFFFFFF" and 
					Overflow = '0') 		--Output check
			Report "Error at Max."							--Report to command line
			Severity ERROR;									--Type of severity to report
			
		--Error Check Overflow 1
		A <= X"FFFFFFFF";										--Set input
		B <= conv_std_logic_vector(1,32);				--Set input
		wait for clock_period;								--Wait for gate delay
		--If not correct then report Error
		Assert ( S = X"00000000" and 
					Overflow = '1' ) 							--Output check
			Report "Error at Overflow 1."					--Report to command line
			Severity ERROR;									--Type of severity to report

		--Error Check Overflow 2
		A <= X"FFFFFFFF";										--Set input
		B <= X"FFFFFFFF";										--Set input
		wait for clock_period;								--Wait for gate delay
		--If not correct then report Error
		Assert ( S = X"FFFFFFFE" 
					and Overflow = '1' ) 					--Output check
			Report "Error at Overflow 2."					--Report to command line
			Severity ERROR;									--Type of severity to report

		--Error Check for ranged additions
		for N in 0 to 1024 loop
			for M in 1024 downto 0 loop
				A <= conv_std_logic_vector(N,32);				--Set input to N with 32 bit range
				B <= conv_std_logic_vector(M,32);				--Set input to M with 32 bit range
				wait for clock_period;								--Wait for gate delay
				--If not correct then report Error
				Assert ( S = conv_std_logic_vector(N+M,32) and 
							Overflow = '0' ) 		--Output check with N+M value
					Report "Error at" &
							 " A=" & integer'image(N) &			--Print strings and N,M, N+M to
							 " B=" & integer'image(M) &			--  counsole upon error.
							 " S=" & integer'image(N+M) &
							 "."--Report to command line
					Severity ERROR;									--Type of severity to report
			end loop;
		end loop;
	--Systems runs for (10ns)*(3+(N+1)*(M+1))= ? ns
		
	Report "Completed Testbench." Severity NOTE; 		--Report testbench complete.
   wait;
   end process;

END;