LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY shift32_tb IS
END shift32_tb;
 
ARCHITECTURE behavior OF shift32_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT shift32
    PORT(
         A : IN  std_logic_vector(31 downto 0);
         B : IN  std_logic_vector(31 downto 0);
         S : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic_vector(31 downto 0) := (others => '0');
   signal B : std_logic_vector(31 downto 0) := (others => '0');
 	--Outputs
   signal S : std_logic_vector(31 downto 0);
	--Clock
	signal clock : std_logic := '0';
	constant clock_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: shift32 PORT MAP (
          A => A,
          B => B,
          S => S
        );

	-- Clock Process
	clock_process : process
		begin
			clock <= '0';
			wait for clock_period/2;
			clock <= '1';
			wait for clock_period/2;
	end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 10 ns.
		A <= X"00000000";
		B <= X"00000000";
      wait for 10 ns;

      -- insert stimulus here
		
		--Error Check 0
		A <= X"FFFFFFFF";							--Set input
		B <= X"00000004";							--Set input
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( S = X"FFFFFFF0" ) 			--Output check
			Report "Error 0: S = xFFFFFFF0" 	--Report to command line
			Severity ERROR;						--Type of severity to report
			
		--Error Check 1
		A <= X"0F0F0F0F";
		B <= X"00000008";
		wait for clock_period;
		Assert ( S = X"0F0F0F00" )
			Report "Error 1: S = x0F0F0F00"
			Severity ERROR;
			
		--Error Check 2
		A <= X"FFFFFFFF";
		B <= X"00000020";
		wait for clock_period;
		Assert ( S = X"00000000" )
			Report "Error 2: S = x00000000"
			Severity ERROR;
			
	Report "Completed Testbench." Severity NOTE; 		--Report testbench complete.	
   wait;
   end process;

END;