LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
 
ENTITY mux4_tb IS
END mux4_tb;
 
ARCHITECTURE behavior OF mux4_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT mux4
    PORT(
         A : IN  std_logic_vector(31 downto 0);
         B : IN  std_logic_vector(31 downto 0);
         C : IN  std_logic_vector(31 downto 0);
         D : IN  std_logic_vector(31 downto 0);
         Sel : IN  std_logic_vector(1 downto 0);
         S : OUT  std_logic_vector(31 downto 0)
        );
    END COMPONENT;
    
   --Inputs
   signal A : std_logic_vector(31 downto 0) := (others => '0');
   signal B : std_logic_vector(31 downto 0) := (others => '0');
   signal C : std_logic_vector(31 downto 0) := (others => '0');
   signal D : std_logic_vector(31 downto 0) := (others => '0');
   signal Sel : std_logic_vector(1 downto 0) := (others => '0');
 	--Outputs
   signal S : std_logic_vector(31 downto 0);
	--Clock
	signal clock : std_logic := '0';
	constant clock_period : time := 20 ns;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: mux4 PORT MAP (
          A => A,
          B => B,
          C => C,
          D => D,
          Sel => Sel,
          S => S
        );

	-- Clock Process
	clock_process : process
		begin
			clock <= '0';
			wait for clock_period/2;
			clock <= '1';
			wait for clock_period/2;
	end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
     -- hold reset state for 10 ns.
		A <= X"00000000";
		B <= X"00000000";
		C <= X"00000000";
		D <= X"00000000";
		Sel <= "00";
      wait for 10 ns;

      -- insert stimulus here
		
		--Error Check A
		A <= X"00000001";							--Set input A
		B <= X"00000002";							--Set input B
		C <= X"00000003";							--Set input C
		D <= X"00000004";							--Set input D
		Sel <= "00";								--Set input Sel
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( S = A ) 							--Output check
			Report "Error: S = A" 				--Report to command line
			Severity ERROR;						--Type of severity to report

		--Error Check B
		A <= X"12345678";							--Set input A
		B <= X"9ABCDEF0";							--Set input B
		C <= X"FEDCBA90";							--Set input C
		D <= X"87654312";							--Set input D
		Sel <= "01";								--Set input Sel
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( S = B ) 							--Output check
			Report "Error: S = B" 				--Report to command line
			Severity ERROR;						--Type of severity to report
			
		--Error Check C
		A <= X"AAAAAAAA";							--Set input A
		B <= X"BBBBBBBB";							--Set input B
		C <= X"CCCCCCCC";							--Set input C
		D <= X"DDDDDDDD";							--Set input D
		Sel <= "10";								--Set input Sel
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( S = C ) 							--Output check
			Report "Error: S = C" 				--Report to command line
			Severity ERROR;						--Type of severity to report
			
		--Error Check D
		A <= X"89ABCDEF";							--Set input A
		B <= X"FEDCBA00";							--Set input B
		C <= X"12345678";							--Set input C
		D <= X"ABCD0DEF";							--Set input D
		Sel <= "11";								--Set input Sel
		wait for clock_period;					--Wait for gate delay
		--If not correct then report Error
		Assert ( S = D ) 							--Output check
			Report "Error: S = D" 				--Report to command line
			Severity ERROR;						--Type of severity to report
	
	Report "Completed Testbench." Severity NOTE; 		--Report testbench complete.	
   wait;
   end process;

END;