library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity checkerboard is Port ( Clock : in std_logic; Reset : in std_logic; Size : in std_logic_vector(1 downto 0);--switches Hsync : out std_logic;--vga signals Vsync : out std_logic; R : out std_logic;--color signals G : out std_logic; B : out std_logic ); end checkerboard; architecture struct of checkerboard is component vga_timings is port( Reset : in std_logic; Clock : in std_logic; -- 50MHz clock assumed Hsync : out std_logic; Vsync : out std_logic; Hcount : out std_logic_vector(9 downto 0); --Might need to change range based on design Vcount : out std_logic_vector(8 downto 0) --Might need to change range based on design ); end component; component memory is Port ( WE : in std_logic; EN : in std_logic; SSR : in std_logic; CLK : in std_logic; ADDR: in std_logic_vector(13 downto 0); DI : in std_logic_vector(0 downto 0); DO : out std_logic_vector(0 downto 0) ); end component; signal hcount_sig : std_logic_vector(9 downto 0); --Might need to change range based on design signal vcount_sig : std_logic_vector(8 downto 0); --Might need to change range based on design signal posx : std_logic_vector(9 downto 0); --Might need to change range based on design signal posy : std_logic_vector(8 downto 0); --Might need to change range based on design signal memory_address : std_logic_vector(13 downto 0); signal color : std_logic_vector(0 downto 0); --Deependant on memory begin my_vga: vga_timings port map( Reset => Reset, Clock => Clock, Hsync => Hsync, Vsync => Vsync, Hcount => Hcount_sig, Vcount => Vcount_sig ); checkerboard_memory: memory port map( WE => '0', --always reading, never writing EN => '1', --always keep memory on SSR => '0', CLK => Clock, ADDR => memory_address, --generated in bottom process DI => "0", --dummy value, DO => color ); --memory address generation based on the 'size' switches process(size) begin case size is when "00" => memory_address <= vcount_sig(5 downto 0) & "00" & hcount_sig(5 downto 0); when "01" => memory_address <= vcount_sig(6 downto 1) & "00" & hcount_sig(6 downto 1); when "10" => memory_address <= vcount_sig(7 downto 2) & "00" & hcount_sig(7 downto 2); when "11" => memory_address <= vcount_sig(8 downto 3) & "00" & hcount_sig(8 downto 3); when others => memory_address <= (others => '0'); --just zero out the address end case; end process; --set our color signals here based on the output of memory R <= color(0); G <= color(0); B <= color(0); end struct;