My current research effort focuses on the design technology for embedded systems and other systems utilizing non-traditional architectures.  The target applications include automotive control, manufacturing automation, network switches, home appliance, cellular phones, Personal Digital Assistants, internet appliances, pacemakers, weapons, and toys.  The underlying architecture may consists of microprocessor, micro-controller, digital signal processor, or application specific integrated circuits.  Design of embedded systems can be subject to many different types of constraints, including timing, size, weight, power consumption, reliability, and cost.  I am interested in answering the following four questions:

1) How do I go about designing a <insert your favorite embedded system here>?

2) How much can I get my computer to help me to achieve an implementation?

3) How do I make sure that my implementation really works?

4) How do I know my implementation is the best?

Selected Publications

Design Framework

...or how design is done

M. Chiodo, P. Giusto, A. Jurecska, L. Lavagno, H. Hsieh, and A. Sangiovanni-Vincentelli. 1993.  A Formal Specification Model for Hardware/Software Co-design.  In Proceedings of the International Workshop on Hardware-Software Co-design, 15 pages

M. Chiodo, P. Giusto, A. Jurecska, H. Hsieh, A. Sangionvanni-Vincentelli, and L. Lavagno. 1994.  Hardware/Software Co-design of Embedded Systems. IEEE Micro, 14(4):  26-36.

L. Lavagno, M. Chiodo, P. Giusto, H. Hsieh, S.Yee, A. Jurecska, and A. Sangiovanni-Vincentelli.  1994.  A Case Study in Computer-Aided Co-Design of Embedded Controllers.  In Proceedings of the International Workshop on Hardware-Software Co-design, pp. 220-224.

L. Lavagno, A. Sangiovanni-Vincentelli, and H. Hsieh.  1995.  Models and Algorithms for Embedded System Synthesis and Validation. In G. De Micheli, editor, NATO Advanced Study Institute. Kluwer Academic Publisher, pp. 213-242.

M. Chiodo, D. Engels, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, K. Suzuki, and A. Sangiovanni-Vincentelli. 1996.  A Case Study in Computer-Aided Co-design of Embedded Controllers. Design Automation for Embedded Systems. 1(1-2): 51-67.

 F. Balarin, M. Chiodo, H. Hsieh, B. Tabbara, A. Sangiovanii-Vincentelli, A. Jurecska, K. Lavagno, C. Passerone, and K. Suzuki.  1997.  Hardware-Software Co-Design of Embedded Systems: the Polis Approach. Kluwer Academic Publishers, Boston; Dordrecht, pp. 1-291.

H. Hsieh.  2000.  Formal Methods for Embedded System Design.  PhD Thesis, University of California Berkeley,. Memorandum No. UCB/ERL M00/37, pp.1-147.

F. Balarin, H.. Hsieh, L. LavagnoC. Passerone, A. Sangionvanni-Vincentelli, and Y. Watanabe. April, 2003.  Metropolis: An Integrated Electronic System Design Environment  IEEE Computer. Volume 6, Number 4. pp. 45-52.

S. Cotterell, F. Vahid, W. Najjar, H. Hsieh.  October, 2003.  First Results with eBlocks: Embedded Systems Building Blocks.  First International Conference on Hardware/Software Codesign & System Synthesis. pp. 168-175

F. Vahid, H. Hsieh, and S. Cotterell.  A Boolean Digital Abstraction for Sensor Networks.  Submitted to Design Automation and Test in Europe, 2005.

Synthesis 

...or how to automate design process

M. Chiodo, P. Giusto, A. Jurecska, L. Lavagno, H. Hsieh, K. Suzuki, A. Sangiovanni-Vincentelli and E. Sentovich.  1995.  Synthesis of Software Programs for Embedded Control Applications. In Proceedings of the Design Automation Conference, pp. 578-592.

F. Balarin, M. Chiodo, P. Giusto, H. Hsieh, A. Jurecska, L. Lavagno, A. Sangiovanni-Vincentelli, E. Sentovich, and K. Suzuki.  1999. Synthesis of Software Programs for Embedded Control Applications. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, 18(6):  834-849.

R. Mannion, H. Hsieh, S. Cotterell, F. Vahid.  System Synthesis for Networks of Programmable Blocks  Submitted to Design Automation and Test in Europe, 2005.

Verification 

...or how to validate an implementation

H. Hsieh, L. Lavagno, C. Passerone, C. Sansoe, and A. Sangiovanni-Vincentelli.  1997.  Modeling Micro-Controller Peripherals1 for High-level Co-Simulation and Synthesis. In Proceedings of the International Workshop on Hardware-Software Co-design, pp. 127-130.

X. Chen, F. Chen, H. Hsieh, F. Balarin, and Y. Watanabe,. 2002.  Formal Verification of Embedded System Designs at Multiple Levels of Abstraction.  In Proceedings of the International Workshop on High Level Design, Validation, and Test.  pp.125-130.

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe.  Mar, 2003.  Automatic Generation of Simulation Monitors from Quantitative Constraint Formula.  In Proceedings of the conference on Design Automation and Test in Europe. pp. 1174-1175.

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe.  June, 2003.  Simulation Trace Verification for Quantitative Constraints.  In Embedded Software for SoC, Kluwer Academic Publisher. pp. 275-286.

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe.  June, 2003.  Case Studies of Model Checking for Embedded System Designs.  In Proceedings of the conference on Application of Concurrency to System Design. 9 pages.

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe.  June, 2003.  Automatic Trace Analysis for Logic of Constraints.  In Proceedings of the Design Automation Conference. pp. 460-465.

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe.  June, 2003.  Formal Verification for Embedded System Designs.  In Journal of Design Automation for Embedded Systems, Special Issue of Covalidation of Embedded Hardware/Software System. pp. 139-153.

X. Chen, H. Hsieh, F. Balarin, and Y. Watanabe.  Nov, 2003.  Verifying LOC Based Functional and Performance Constraints.  In Proceedings of the International Workshop on High Level Design, Validation, and Test.  pp 83-88.

X. Chen, H. Hsieh, F. Balarin, Y. Watanabe.  August, 2004.  Logic of Constraints: A quantitative Performance and Functional Constraint Formalism.  pp 1243-1255.

X. Chen, Y. Luo, H. Hsieh, L. Bhuyan, F. Balarin.  February, 2004.  Utilizing Formal Assertions for System Design of Network Processors.  Vol 3 pp. 126-131.

J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, F. Balarin.  To appear in November 2004.  Assertin-Based Power/Performance Analysis of Network Processor Architectures. 6 pages.

X. Chen, H. Hsieh, F. Balarin.  Formal System Level Abstraction Propagation in Metropolis.  Submitted to Design Automation and Test in Europe, 2005.

X. Chen, A. Davare, H. Hsieh, A. Sangiovanni-Vincentelli, Y. Watanabe.  Simulation Based Deadlock Analysis for System Level Designs.  Submitted to Design Automation and Test in Europe, 2005.

X. Chen, Y. Luo, H. Hsieh, L. Bhuyan, F. Balarin.  Assertion Based Verification and Analysis of Network Processor Architectures. Submitted to Design Automation for Embedded Systems, 2004.

Design Exploration 

...or how to get to the best design

H. Hsieh, F. Balarin, L. Lavagno, and A. Sangiovanni-Vincentelli.  2000.  Efficient Methods for Embedded System Design Space Exploration. In Proceedings of the Design Automation Conference, pp. 607-612.

H. Hsieh, A. Sangiovanni-Vincentelli, F. Balarin, and L. Lavagno.  2000.  refining Abstract Equivalence Analysis for Embedded System Design.  In Proceedings of the International Workshop on High Level Design, Validation, and Test, pp. 139-146.

H. Hsieh, F. Balarin, and A. Sangiovanni-Vincentelli. 2001.  Synchronous Equivalence: Formal Methods for Embedded Systems. Kluwer Academic Publishers, Boston; Dordrecht, pp. 1-129.  

H. Hsieh, F. Balarin, H. Hsieh, L. Lavagno, A. Sangiovanni-Vincentelli.  2001. Synchronous Approach to the Functional Equivalence of Embedded System Implementations. IEEE Transactions on Computer-Aided Design of Intergrated Circuits and Systems, 20(8):  1016-1033.

J. Yu, W. Wu, X. Chen, H. Hsieh, J. Yang, F. Balarin.  Assertion Based Automatic Design Exploration of DVS in Network Processor Architectures.  Submitted to Design Automation and Test in Europe, 2005.

S. Cotterell, F. Vahid, H. Hsieh.  Multi-layered Compute/Communication Codesign for Sensor-Network Systems.  Submitted to Design Automation and Test in Europe, 2005.