UCR CS269: Hardware/Software Engineering of Embedded Systems

CS269 deals with the exciting and rapidly-growing field of embedded computing systems.  The course will present state-of-the-art software and hardware design techniques for embedded computing systems.  Topics include specification models, languages, simulation, partitioning algorithms, estimation methods, model refinement, and design methodology.  

Course information

Class Readings and Presentation

You are expected to read assigned readings before the date they are presented, to attend classes and actively participate in discussions.  You are also expected to present several papers during the quarter, for which you should study thoroughly, and do outside research as necessary.  Questions will be posed in class about the material and you are expected to be able to answer them.  Presentation slides are provide of which you need to understand thoroughly.  You are free to contact authors to answer any questions you might have.  You must properly acknowledge the source so there won't be questions of plagiarism.

List of papers:

Individual Projects

Project should be done individually.  You are encouraged to propose your own project, possibly related to your Ph.D., M.S. thesis work or even B.S. senior project work.  The idea is that it may, with possibly one more quarter of independent study work, become a submission to a workshop and/or a chapter in your thesis.  The content should falls somewhat within the broad confine of the course and has comparable depth as the other projects.  A list of potential project will also be available at the beginning of the class.  Project request is on a first-come-first-serve basis.  You are encouraged to send me e-mail frequently about your progress or any question you may have throughout the quarter.  

Project Deadlines are: 

1) Interactive RTL-Gate Mapping Rule Wizard

2) Effective and Efficient RTL-Gate Mapping Engine

3) Combinational RTL-Gate Correlation Engine

4) Automatic RTL-Gate Incremental Synthesis for Engineering Change Order

5) Formal and Semi-Formal Technique for RTL-Gate Correlation

6) A practical C++-to-VHDL Translator

7) Jpeg decoder energy analysis

8) MPSoC Energy Analysis

9) Simulation Deadlock Analysis for SystemC Designs

10) TBA

Project Descriptions

1) Interactive RTL-gate mapping rule wizard

Goal:

Correlating objects from different levels of abstraction for a design has become critical in design verification and debugging. Logic synthesis tools takes a design description in Register Transfer Level (RTL) and synthesize it down to the gate level description through structural transformation, while preserving some name patterns especially for sequential objects.  Since not all the naming are preserved, one of the techniques to correlate RTL description to gate level description use heuristic renaming rules based on prefix and suffix string matching.  This mapping is far from perfect and user-specified renaming rules can be used to improve the accuracy of these mapping.  This project aims to design a wizard tool to assist the user in analyzing the mapping and designing a set of specific renaming rules to improve the mapping when correlating large designs.

Procedure:

1.        Study and understand the logic synthesis process and its common transformations (e.g. Synopsys Design Compiler).

2.        Study and understand the current gate-to-RTL correlation technique including heuristic prefix/suffix string matching, Longest-common-subsequence (LCS) algorithms, Levenshtein-distance, and other “spell checking” algorithm such as Wagner-Fisher.

3.        Study and understand user-specified renaming rules for the gate-to-RTL correlation, focusing on regular expressions, hierarchy changes, and their combinations.  Study their effects on the overall correlation results.

4.        Compare (possibly with diff or xdiff) the objects from both levels of abstraction that are not yet mapped, starting from a possibly non-empty list of objects that have already been mapped. For large designs, it is only possible to analyze and display a subset of object at a time (may be different subsets), investigate into how such subsets are chosen. 

5.        In an interactive setting, user adds or changes renaming rules incrementally.  Analyze and present the effect of the change.  Specifying one rule at a time can be very tedious, design an engine so that multiple rules can be specified and represent effectively.

6.        (Bonus) automatically suggest additional rules to improve the results by analyzing the objects and current rules as they are specified (possibly using machine learning techniques).

Expected Product:

Propose a practical usage flow for the interactive rule mapping wizard, including metrics for global mapping and local mapping, display of mapped and unmapped object, and “macros” for ease of rule specifications.

2) Effective and efficient RTL-gate mapping engine

Goal:

Correlating objects from different levels of abstraction for a design has become critical in design verification and debugging. Logic synthesis tools takes a design description in Register Transfer Level (RTL) and synthesize it down to the gate level description through structural transformation, while preserving some name patterns especially for sequential objects.  Since not all the naming are preserved, one of the techniques to correlate RTL description to gate level description use heuristic renaming rules based on prefix and suffix string matching.  This project aims to implement an effective mapping engine to perform such a mapping for large design.  It has to be efficient since realistic designs contain astronomical number of design objects. Heuristics of a very low computational complexity is crucial.

Procedure:

1.        Study and understand the logic synthesis process and its common transformations (e.g. Synopsys Design Compiler).

2.        Study and understand the current gate-to-RTL correlation technique including heuristic prefix/suffix string matching, Longest-common-subsequence (LCS) algorithms, Levenshtein-distance, and other “spell checking” algorithm such as Wagner-Fisher.  Understand regular expression and how hierarchy can naturally exist in a design.  Understand the correlation metrics.

3.        Starting with a give correlation engine (will be provided), analyze the “goodness” of the engine quantitatively.  Propose additional mapping algorithms to improve the mapping.  Implement the algorithms.

4.        Show that your tool indeed improves the mapping through realistic, industrial size designs.

5.        (Bonus) Is 100% mapping possible for all design? What is a reasonable metric for 100% mapping?  Can 100% mapping be achieved in reasonably low computation time?

Expected Product:

Propose an improvement to the existing automatic mapping engine.  Demonstrate the improvement through industrial size example.

3) Combinational RTL-gate correlation engine

Goal:

                At the RTL level, combinational circuits are usually modeled as programming statements such as arithmetic operations and conditional statements. After synthesized to the gate level, these objects are modeled as combinational gates and nets. Due to the optimization present in state-of-the-art logic synthesis tool, a combinational object at the gate level, may not have an exact correspondence at the RTL level. In this project, we assume sequential objects such as registers and latches are correlated exactly. Therefore, the work remains to correlated combinational blocks between sequential boundaries. The goal is to correlate an RTL statement to a minimum set of gates and a gate to a minimum set of RTL statement, given a typical industrial design. Different RTL language constructs are handled differently in the synthesis, so should they be studied case by case in correlation.

Procedure:

1.        Study and understand the logic synthesis process and its common transformations (e.g. Synopsys Design Compiler).

2.        Study and understand the current gate-to-RTL correlation technique and its limitations.

3.        Study RTL level HDL language constructs and their synthesis algorithms for combinational objects, such as arithmetic operations, if-else statements, case statements, assignment, and etc. For each category of objects, propose a correlation mechanism to the gate level objects. Devise the metric for correlation and keep in mind that the mapping will not be exclusive (multiple RTL statements correlate to the same gate).  How does sharing and common sub-expression extraction affect the correlation?

4.        Correlate individual gate to RTL statements that may “have something to do with” the gate. Devise metric for correlation.

5.        (bonus) Can we scarify optimality in design for 100% RTL to gate correlation?  What’s the cost?  Justify your answer.

Expected Product:

                A correlation engine for RTL->gate on a statement on a statement by statement basis, and a correlation engine for gate->RTL on a gate by gate basis.

4) Automatic RTL-gate incremental synthesis for Engineering Change Order (ECO)

Goal:

                This is a further research project based on gate-to-RTL correlation including both sequential objects and combinational objects. Sometime the user would like to change a small part of the design without going through the entire tool flow once again at the late design stage. The process is called engineering change order (ECO). This project focuses on automatic gate level netlist modification from the change in RTL design.

Procedure:

1.        Study and understand the logic synthesis process and its common transformations (e.g. Synopsys Design Compiler).

2.        Study and understand the current gate-to-RTL correlation technique and its limitations.

3.        Identify and study possible ECO changes at the RTL level.

4.        Propose automatic mechanism and algorithms for netlist modification from RTL ECO changes based on current RTL-to-gate correlation technique.  Implement the incremental synthesis algorithm. You may consider simple mapping from RTL-gate.  Demonstrate it on a realistic industrial example.

5.        (bonus) When should an incremental synthesis take place and when is re-synthesis of the entire design preferable?  Is simple RTL-gate transformation (i.e. no fancy logical synthesis technique) always possible and what is the cost, in term of being suboptimal, may it be?

Product:

                An effective automatic mechanism for gate level netlist modification from the elemental changes in the RTL design.

5) Formal and semi-formal technique for RTL-gate correlation

Goal:

                The current design correlation technique relies on user-specified renaming rules and heuristic name changes to perform the correlation rather than formal methods due to performance issues. But it also introduces possible inaccuracy by possibly correlating two objects that are not exact correspondence, which will make the later-on verification or debugging process error-prone. This project is to propose an effective but still efficient technique to verify the correctness of the design correlation with formal or semi-formal methods.  The idea is to start with correlation, and apply formal and semi-formal method locally to keep the complexity under check.

Procedures:

1.        Study and understand the logic synthesis process and its common transformations (e.g. Synopsys Design Compiler).

2.        Study the current gate-to-RTL correlation technique. Understand its limitation that may introduce inaccuracy in the correlation results.

3.        Study the efficiency and effectiveness of current equivalence checking engines (e.g. Synopsys Formality)

4.        Study possible techniques or their combinations that can be used to verify the correctness of the correlation including both formal and semi-formal techniques, which include but are not limited to local equivalence checking and random simulation.  Implement a simple tool/script and test it out on a large industrial design.

5.        (bonus) Analysis the theoretical value of correlation, and correlation follow by equivalence.  How much of the correlation do we have to be declare “correct” and how much more equivalence checking we will need in order to declare equivalence in entirety?

Expected Product:

Propose a practical solution for the verification of design correlation between different levels of abstraction. Implement a simple tool/script that can “call” correlation and equivalence engine appropriately.

6) A practical C++-to-VHDL translator

Goal:

DSP algorithm is usually developed and written in C/C++ code. When such DSP algorithm is implemented in hardware as a purely hardware implementation, a part of a hw/sw solution, or an FPGA implementation, a manual translation into VHDL/Verilog is usually required.  Such a manual translation is obviously tedious and error prone.  Translation of some of the constructs are obviously straight-forward (e.g. addition, substraction, variable declaration, loop, branch), but sometime it could be entirely non-trivial (e.g. pointer reference, classes, library, dynamic memory allocation). While a couple of recently developed commercial tools may be available for such a task (e.g. Forte, Celoxica),  we want to know exactly what it take to do such a translation automatically and efficiently.
In this project, you will write the translator that will work well at least for the specific example C++ code. There are several commercial and academic tools available, such as Impulse CoDeveloper and Spark, which can be used as reference. It is recommended to use existing frontend, such as gcc, to save some work and have more time for VHDL backend generator.

Procedure

1. Convert given C++ program to VHDL by hand to understand what have to be done.
2. Research existing C-to-VHDL generators and C frontends
3. Write C-to-VHDL generator for specific examples

Expected Product:

A working translator for given C++ code segment

7) Jpeg decoder energy analysis (or any other data-centric application)