Notes

Outline

Hardware /Software Instruction Set Configurability for System-on-Chip Processors

Introduction Configurable and extensible processor architectures offer the efficiency of tuned logic solutions with the flexibility of standard high-level programming methodology. Designing at the level of software and instructions set architecture significantly shortens the design cycle and reduces verification effort and risk.

Why Configure Processors? Continuing growth in silicon chip capability is reducing the number of chips in a typical system, and magnifying the size, performance and power benefits of system-on-chip integration. Newer electronic products demand better cost, bandwidth, battery life, and software functionality. Application-specific processor cores promise a combination of full software flexibility with high efficiency.

What’s the Right Architecture? A system with a processor and a coprocessor can have its performance improved by integrating the coprocessor. System architect can discard external control logic: the finite state machines and micro-sequencers. Faster instruction set extension and performance testing allows for rapid prototype validation and experimentation. Simplifies the use of data memory, since the processor can share a unified data memory.

Extension Description Medthod Instruction format and encoding. field : gives a name to a group of bits in the instruction word. opcode : assigns instruction fields with values. operand : specifies how instruction operand is encoded in an instruction field. iclass : defines the assembly format for an instruction.

"Example:" Example: /*Define new opcodes*/ opcode A4 op2=0 CUST0 opcode S4 op2=1 CUST0 /*Define new assembly class*/ iclass RR{A4,S4}{out arr, in ars, in art} /* Define new assembly instructions*/ A4 arr, ars, art S4 arr, ars, art

"Customized Datapath" Customized Datapath Computation part of an instruction is specified in a TIE reference block, which contains a series of assignment statements. Syntax is very close to Verilog.

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"A semantic statement can be..." A semantic statement can be used to optimize the code for hardware.

"Multi-cycle instructions" Multi-cycle instructions TIE provides a simple schedule construct to capture the multi-cycle instructions requirements. Example: acc =  acc + a * b; schedule MAC_SCHED {MAC} { use a 1; use b 1; use acc 2; def acc 2; }

"TIE states allow instructions to..." TIE states allow instructions to have many more sources and destinations than they are provided by the read and write ports of the core register files. They can be as analogous to the processor status registers or states in FSM. States can hold values for temporary variables during program execution.

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"Designer may also add register..." Designer may also add register files. Ex.

Software Support TIE compiler automatically modify/generate the Xtensa C/C++ compiler, assembler, simulator, debugger, os, and application libraries when a TIE instruction is added. Every TIE instruction is directly accessible in C or C++ via intrinsic function.

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