•Module FSM4(input logic serial, clock, reset);
• State {S0, S1, S2 }
currentState;
• Always_ff @ (postdge clock iff
!reset)
• transition
(currentState)
• S0: if (serial ==1 )
->> S2;
• S2: if (serial ==0 )
->> S1;
• else
->>S0;
• S1: ->>
S0 n = find(“a”, root);
• endtransition
•Endmodule