Notes

Outline

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Outline SUPERLOG Introduction Why SUPERLOG Language conponents Streamlined methodology Language Evolution Code fragments Datatype System Interfaces

Why SuperLog

Why SuperLog Thinking of a single language for four purposes: Describe hardware in C is difficult Verilog is poor as a general-purpose programming language. No dynamic memory allocation Poor built-ininput and text processing is extremely difficult VHDL also hampered by three problems

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Unifying Language Components

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SUPERLOG –Building on Verilog

SUPERLOG –Building on Verilog

SUPERLOG –Building on Verilog

SUPERLOG code fragment Module FSM4(input logic serial, clock, reset); State {S0, S1, S2 } currentState; Always_ff @ (postdge clock iff !reset) transition (currentState) S0: if (serial ==1 ) ->> S2; S2: if (serial ==0 ) ->> S1; else ->>S0; S1: ->> S0  n = find(“a”, root); endtransition Endmodule

Learning SUPERLOG Module FSM4(input logic serial, clock, reset);   State {S0, S1, S2 } currentState;   Always_ff @ (postdge clock iff !reset) transition (currentState) S0: if (serial ==1 ) ->> S2; S2: if (serial ==0 ) ->> S1; else ->>S0; S1: ->> S0  n = find(“a”, root); endtransition Endmodule

Module

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Datatypes

Timescales Time constant Legal time units Are s, ms, us, ns, ps, fs Time Rules

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