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CS269: HW/SW Engineering of Embedded Systems, Winter02
Architecture
•Architecture: abstracted layers for smooth refinement
SYSTEM:
   - SW modules, HW
   - bounded FIFO, lossy channels
   - no address, bus independent
TRANSACTION:
   - address, data split in chunk
   - no detailed bus protocol or width
PHYSICAL:
  - specific bus protocol
  - detailed RTOS characterization
CPU
ASIC2
ASIC1
Sw1
Hardware
module
Sw2
Sw I/F
Channel I/F
Wrappers
Hw
Bus I/F
C-Ctl
Channel Ctl
B-I/F
CPU-IOs
e.g. PIBus 32b
e.g. OtherBus 64b...
C-Ctl
RTOS